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  1. No Access

    Book

  2. Chapter and Conference Paper

    Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs

    Low-voltage scaling limitations of nanoscale CMOS LSIs are one of the major problems in the nanoscale era because they cause the evermore-serious power crises with device scaling. The problems stem from two un...

    Kiyoo Itoh in Integrated Circuit and System Design. Powe… (2011)

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    Book

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    Chapter

    High-Voltage Tolerant Circuits

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

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    Chapter

    Variability Issue in the Nanometer Era

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

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    Chapter

    Ultra-Low Voltage Nano-Scale DRAM Cells

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

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    Chapter

    Leakage Reduction for Logic Circuits in RAMs

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

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    Chapter

    Reference Voltage Generators

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

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    Chapter

    Voltage Up-Converters and Negative Voltage Generators

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

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    Chapter

    An Introduction to LSI Design

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

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    Chapter

    Ultra-Low Voltage Nano-Scale SRAM Cells

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

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    Chapter

    Voltage Down-Converters

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

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    Chapter

    Memory Leakage Reduction

    Takayuki Kawahara, Kiyoo Itoh in Leakage in Nanometer CMOS Technologies (2006)

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    Chapter and Conference Paper

    Low-Voltage Embedded RAMs – Current Status and Future Trends

    Low-voltage high-density embedded (e-) RAMs, focusing on RAM cells and peripheral circuits, are described. First, challenges and trends in low-voltage e-RAMs are described based on the S/N issue of RAM cells, ...

    Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara in Integrated Circuit and System Design. Powe… (2004)

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    Chapter

    Ultralow-Voltage Memory Circuits

    The key design issues for ultralow-voltage (0.5–2 V) memory circuits are reviewed in terms of stable memory-cell operation, subthreshold current reduction, suppression of or compensation for design-parameter v...

    Kiyoo Itoh in Design of System on a Chip (2004)

  16. Chapter

    Low-Voltage Embedded-RAM Technology: Present and Future

    First, key issues for low-voltage (<1V) embedded RAMs are summarized in terms of stable operation, suppression of leakage (gate-tunneling/subthreshold) currents, and speed variation of memory cells and periphe...

    Kiyoo Itoh, Hiroyuki Mizuno in SOC Design Methodologies (2002)

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    Chapter and Conference Paper

    Trends in Ultralow-Voltage RAM Technology

    This paper describes ultralow-voltage RAM technology for standalone and embedded memories in terms of signal-to-noise-ratio designs of RAM cells and subthreshold-current reduction. First, structures and areas ...

    Kiyoo Itoh in Integrated Circuit Design. Power and Timin… (2002)