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References
D.-S. Min, S. Cho, D. S. Jun, D.-J. Lee, Y. Seok and D. Chin, “Temperature-compensation circuit techniques for high-density CMOS DRAM’s,” IEEE J. Solid-State Circuits, vol. 27, pp. 626–631, Apr. 1992.
K. Itoh, VLSI Memory Design (Baifukan, Tokyo 1994) (in Japanese).
S.-M. Yoo, E. Haq, S.-H. Lee, Y.-H. Choi, S.-I.-Cho, N.-S. Kang and D. Chin, “Variable Vcc design techniques for battery-operated DRAM’s,” IEEE J. Solid-State Circuits, vol. 28, pp. 499–503, Apr. 1993.
H. Hidaka, , K. Arimoto, K. Hirayama, M. Hayashikoshi, M. Asakura, M. Tsukude, T. Oishi, S. Kawai, K. Suma, Y. Konishi, K. Tanaka, W. Wakamiya, Y. Ohno and K. Fujishima, “A 34-ns 16-Mb DRAM with controllable voltage down-converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 1020–1027, July 1992.
P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and design of analog integrated circuits, 4th ed. (John Wiley, New York 2001), Chap. 4.
K. Ishibashi, K. Sasaki and H. Toyoshima, “A voltage down converter with submicroampere standby current for low-power static RAM’s,” IEEE J. Solid-State Circuits, vol. 27, pp. 920–926, June 1992.
M. Horiguchi, M. Aoki, J. Etoh, H. Tanaka, S. Ikenaga, K. Itoh, K. Kajigaya, H. Kotani, K. Ohshima and T. Matsumoto, “A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier,” IEEE J. Solid-State Circuits, vol. 25, pp. 1129–1135, Oct. 1990.
R. A. Blauschild, P. A. Tucci, R. S. Muller and R. G. Meyer, “A new NMOS temperature-stable voltage reference,” IEEE J. Solid-State Circuits, vol. SC-13, pp. 767–773, Dec. 1978.
M. Horiguchi, M. Aoki, J. Etoh, K. Itoh, K. Kajigaya, A. Nozoe and T. Matsumoto, “Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test,” IEEE J. Solid-State Circuits, vol. 26, pp. 1544–1549, Nov. 1991.
H. Tanaka, Y. Nakagome, J. Etoh, E. Yamasaki, M. Aoki and K. Miyazawa, “Sub-1-$UPmu$A dynamic reference voltage generator for battery-operated DRAM’s,” IEEE J. Solid-State Circuits, vol. 29, pp. 448–453, Apr. 1994.
B. Razavi, Design of Analog CMOS Integrated Circuits, (McGraw-Hill, 2001), Chap. 11.
B.-S. Song and P. R. Gray, “A precision curvature-compensated CMOS bandgap reference,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 634–643, Dec. 1983.
K. E. Kuijk, “A precision reference voltage source,” IEEE J. Solid-State Circuits, vol. SC-8, pp. 222–226, June 1973.
A. P. Brokaw, “A simple tree-terminal IC bandgap reference,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 388–393, Dec. 1974.
D. Burnett, K. Erington, C. Subramanian and K. Baker, “Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits,” in Symp. VLSI Technology Dig. Tech. Papers, June 1994, pp. 15–16.
Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S.-H. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind and H.-S. Wong, “CMOS scaling into the nanometer regime,” Proc. IEEE, vol. 85, pp. 486–504, Apr. 1997.
X. Tang, V. De and J. Meindl, “Intrinsic MOSFET parameter fluctuations due to random dopant placement,” IEEE Trans. VLSI Systems, vol. 5, pp. 369–376, Dec. 1997.
H. Neuteboom, B. M. J. Kup and M. Janssens, “A DSP-based hearing instrument IC,” IEEE J. Solid-State Circuits, vol. 32, pp. 1790–1806, Nov. 1997.
H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi and K. Sakui, “A CMOS bandgap reference circuit with sub-1-V operation,” IEEE J. Solid-State Circuits, vol. 34, pp. 670–674, May 1999.
J. C. Lee, I.-C. Chen and C. Hu, “Modeling and characterization of gate oxide reliability,” IEEE Trans. Electron Devices, vol. 35, pp. 2268–2278, Dec. 1988.
R. S. Mao, H. H. Chao, Y. C. Chi, P. W. Chung, C. H. Hsieh, C. M. Lin and hN. C. C. Lu, “A new on-chip voltage regulator for high density CMOS DRAMs,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp. 108–109.
M. Hiraki, K. Fukui and T. Ito, “A low-power microcontroller having a 0.5-$UPmu$A standby current on-chip regulator with dual-reference scheme,” IEEE J. Solid-State Circuits, vol. 39, pp. 661–666, Apr. 2004.
K. Ishibashi, K. Komiyaji, S. Morita, T. Aoto, S. Ikeda, K. Asayama, A. Koike, T. Yamanaka, N. Hashimoto, H. Iida, F. Kojima, K. Motohashi and K. Sasaki, “A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers,” IEEE J. Solid-State Circuits, vol. 29, pp. 411–418, Apr. 1994.
P. K. T. Mok and K. N. Leung, “Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference,” in Proc. CICC, Oct. 2004, pp. 635–642.
K. Fukuda, M. Hiraki, M. Horiguchi, T. Akiba, S. Ichiki and H. Tsunoda, “Voltage generation circuit and semiconductor integrated circuit device,” PCT Publication No. WO/2005/062150, July 2005.
B. Razavi, Design of Analog CMOS Integrated Circuits, (McGraw-Hill, 2001), Chap. 18.
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Itoh, K., Horiguchi, M., Tanaka, H. (2007). Reference Voltage Generators. In: Itoh, K., Horiguchi, M., Tanaka, H. (eds) Ultra-Low Voltage Nano-Scale Memories. Series On Integrated Circuits And Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68853-4_6
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