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References
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, NY, 2001.
Y. Nakagome, M. Horiguchi, T. Kawahara, K. Itoh, “Review and prospects of low-voltage RAM circuits,” IBM J. R & D, vol.47, no. 5/6, pp. 525–552, Sep./Nov. 2003.
Y. Nakagome, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, Y. Kawamoto, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda and K. Itoh, “An experimental 1.5-V 64-Mb DRAM,” IEEE J. Solid-State Circuits, vol.26, pp. 465–472, Apr. 1991.
P. Favrat, P. Deval and M. J. Declercq, “A high-efficiency CMOS voltage doubler,” IEEE J. Solid-State Circuits, vol.33, pp. 410–416, Mar. 1998.
J. F. Dickson, “On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circuits, vol.SC-11, pp. 374–378, June 1976.
J.-T. Wu and K.-L. Chang, “MOS charge pumps for low-voltage operation,” IEEE J. Solid-State Circuits, vol.33, pp. 592–597, Apr. 1998.
T. Myono, A. Uemoto, S. Kawai, E. Nishibe, S. Kikuchi, T. Iijima and H. Kobayashi, “High-efficiency charge-pump circuits with large current output for mobile equipment applications,” IEICE Trans. Electron., vol.E84-C, pp. 1602–1611, Oct. 2001.
R. Pelliconi, D. Iezzi, A. Baroni, M. Pasotti and P. L. Rolandi, “Power efficient charge pump in deep submicron standard CMOS technology,” IEEE J. Solid-State Circuits, vol.38, pp. 1068–1071, June 2003.
C. Lauterbach, W. Weber and D. Römer, “Improvement of boosted charge pumps,” IEEE J. Solid-State Circuits, vol.35, pp. 719–723, May 2000.
R. C. Foss, G. Allan, P. Gillingham, F. Larochelle, V. Lines and G. Shimokura, “Application of a high-voltage pumped supply for low-power DRAM,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp. 106–107.
D.-J. Lee, Y.-S. Seok, D.-C. Choi, J.-H. Lee, Y.-R. Kim, H.-S. Kim, D.-S. Jun and O.-H. Kwon, “A 35ns 64Mb DRAM using on-chip boosted power supply,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp. 64–65.
K. Sato, H. Kawamoto, K. Yanagisawa, T. Matsumoto, S. Shimizu and R. Hori, “A 20ns static column 1Mb DRAM in CMOS technology,” in ISSCC Dig. Tech. Papers, Feb. 1985, pp. 254–255.
Y. Konishi, K. Dosaka, T. Komatsu, Y. Ionue, M. Kumanoya, Y. Tobita, H. Genjyo, M. Nagatomo and T. Yoshihara, “A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode,” IEEE J. Solid-State Circuits, vol.25, pp. 1112–1117, Oct. 1990.
Y. Tsukikawa, T. Kajimoto, Y. Okasaka, Y. Morooka, K. Furutani, H. Miyamoto and H. Ozaki, “An efficient back-bias generator with hybrid pum** circuit for 1.5-V DRAM’s,” IEEE J. Solid-State Circuits, vol.29, pp. 534–538, Apr. 1994.
H. Tanaka, M. Isoda and T. Kawahara, “Nonvolatile memory and processing system,” US Patent No. 6, 781,890, Aug. 2004.
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Itoh, K., Horiguchi, M., Tanaka, H. (2007). Voltage Up-Converters and Negative Voltage Generators. In: Itoh, K., Horiguchi, M., Tanaka, H. (eds) Ultra-Low Voltage Nano-Scale Memories. Series On Integrated Circuits And Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68853-4_8
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