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  1. No Access

    Book

    Ultra-Low Voltage Nano-Scale Memories

    Kiyoo Itoh, Masashi Horiguchi… in Series On Integrated Circuits And Systems (2007)

  2. No Access

    Chapter

    High-Voltage Tolerant Circuits

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

  3. No Access

    Chapter

    Variability Issue in the Nanometer Era

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

  4. No Access

    Chapter

    Ultra-Low Voltage Nano-Scale DRAM Cells

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

  5. No Access

    Chapter

    Leakage Reduction for Logic Circuits in RAMs

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

  6. No Access

    Chapter

    Reference Voltage Generators

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

  7. No Access

    Chapter

    Voltage Up-Converters and Negative Voltage Generators

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

  8. No Access

    Chapter

    An Introduction to LSI Design

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

  9. No Access

    Chapter

    Ultra-Low Voltage Nano-Scale SRAM Cells

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

  10. No Access

    Chapter

    Voltage Down-Converters

    Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka in Ultra-Low Voltage Nano-Scale Memories (2007)

  11. No Access

    Chapter

    Memory Leakage Reduction

    Takayuki Kawahara, Kiyoo Itoh in Leakage in Nanometer CMOS Technologies (2006)

  12. No Access

    Chapter

    Ultralow-Voltage Memory Circuits

    The key design issues for ultralow-voltage (0.5–2 V) memory circuits are reviewed in terms of stable memory-cell operation, subthreshold current reduction, suppression of or compensation for design-parameter v...

    Kiyoo Itoh in Design of System on a Chip (2004)

  13. Chapter

    Low-Voltage Embedded-RAM Technology: Present and Future

    First, key issues for low-voltage (<1V) embedded RAMs are summarized in terms of stable operation, suppression of leakage (gate-tunneling/subthreshold) currents, and speed variation of memory cells and periphe...

    Kiyoo Itoh, Hiroyuki Mizuno in SOC Design Methodologies (2002)

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