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  1. No Access

    Article

    Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102,400 nodes

    Minor-embedding heuristics have become an indispensable tool for compiling problems in quadratically unconstrained binary optimization (QUBO) into the hardware graphs of quantum and CMOS annealing processors. ...

    Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto… in Soft Computing (2021)

  2. No Access

    Chapter and Conference Paper

    Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity

    The emergence of new annealing hardware in the last decade and its potential for efficiently solving NP hard problems in quadratically unconstrained binary optimization (QUBO) by emulating the ground state sea...

    Yuya Sugie, Yuki Yoshida, Normann Mertig… in Theory and Practice of Natural Computing (2018)

  3. Article

    Open Access

    Uncertain behaviours of integrated circuits improve computational performance

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition...

    Chihiro Yoshimura, Masanao Yamaoka, Masato Hayashi, Takuya Okuyama… in Scientific Reports (2015)

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  4. No Access

    Chapter

    Low-Power SRAM

    Today, SRAM is an indispensable device in SoCs. The SRAM is used in processor LSIs as an embedded memory because SRAM has manufacturing process compatibility and performance compatibility to the logic circuits...

    Masanao Yamaoka in Green Computing with Emerging Memory (2013)

  5. No Access

    Chapter

    Electrical Stability (Read and Write Operations)

    In SRAM, read and write are fundamental operations. To ensure the correct operations, the stability analysis is indispensable. In this chapter, electrical stability analysis is explained. In Sect. 3.1, the SRA...

    Masanao Yamaoka, Yasumasa Tsukamoto in Low Power and Reliable SRAM Memory Cell an… (2011)

  6. No Access

    Chapter

    Future Technologies

    The design solution described in Chap. 5 will help the minimum operating voltage (VDDmin) of a general 6T single-port SRAM. However, it will eventually face the limitation of the SRAM VDDmin because of the degrad...

    Koji Nii, Masanao Yamaoka in Low Power and Reliable SRAM Memory Cell and Array Design (2011)

  7. No Access

    Chapter

    Low Power Memory Cell Design Technique

    This chapter describes the low power memory cell design technique. Section 4.1 introduces fundamentals of leakage of SRAM array. In Sect. 4.2, source line voltage control techniques are explained as new design...

    Kenichi Osada, Masanao Yamaoka in Low Power and Reliable SRAM Memory Cell and Array Design (2011)

  8. No Access

    Chapter

    Low-Power Array Design Techniques

    This chapter introduces circuit technologies that enhance electric stability of the cell, the latest technologies that provide moderate timing generation, as well as larger cell stability. In Sect. 5.1, the vo...

    Koji Nii, Masanao Yamaoka, Kenichi Osada in Low Power and Reliable SRAM Memory Cell an… (2011)