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  1. No Access

    Chapter

    Design of SRAM Resilient Against Dynamic Voltage Variations

    This chapter deals with the design of resilient against dynamic voltage and temperature variations. The scaled CMOS SRAM suffers from a voltage margin reduction owing to the rising of the minimum operating v...

    Masahiko Yoshimoto, Yohei Nakata, Yuta Kimi… in VLSI Design and Test for Systems Dependabi… (2019)

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    Chapter

    SRAM-Based Physical Unclonable Functions (PUFs) to Generate Signature Out of Silicon for Authentication and Encryption

    , we demonstrate chip-ID generation schemes using SRAM-based ) for secure system LSIs. An using failure bit addresses is presented first and discussed on how to improve the uniqueness and reliability ...

    Koji Nii in VLSI Design and Test for Systems Dependability (2019)

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    Chapter

    Variations in Device Characteristics

    Ever increasing variability in device characteristics is a major threat to the dependability, since it could give rise to faults and failures in VLSI circuits and systems. The arises from the variation in ,...

    Hidetoshi Onodera, Yukiya Miura, Yasuo Sato… in VLSI Design and Test for Systems Dependabi… (2019)

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    Chapter

    Future Technologies

    The design solution described in Chap. 5 will help the minimum operating voltage (VDDmin) of a general 6T single-port SRAM. However, it will eventually face the limitation of the SRAM VDDmin because of the degrad...

    Koji Nii, Masanao Yamaoka in Low Power and Reliable SRAM Memory Cell and Array Design (2011)

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    Chapter

    Low-Power Array Design Techniques

    This chapter introduces circuit technologies that enhance electric stability of the cell, the latest technologies that provide moderate timing generation, as well as larger cell stability. In Sect. 5.1, the vo...

    Koji Nii, Masanao Yamaoka, Kenichi Osada in Low Power and Reliable SRAM Memory Cell an… (2011)