Abstract
The design solution described in Chap. 5 will help the minimum operating voltage (VDDmin) of a general 6T single-port SRAM. However, it will eventually face the limitation of the SRAM VDDmin because of the degradation of the SRAM stability due to an increase in the local V th variation. In this chapter, first some alternative 6T single-port SRAM cells to enhance the SRAM stability are introduced in Sect. 7.1.
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Nii, K., Yamaoka, M. (2011). Future Technologies. In: Ishibashi, K., Osada, K. (eds) Low Power and Reliable SRAM Memory Cell and Array Design. Springer Series in Advanced Microelectronics, vol 31. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19568-6_7
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DOI: https://doi.org/10.1007/978-3-642-19568-6_7
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