1 Introduction

In order to improve the country's comprehensive national strength and seize space resources, the space activities include space technology, space applications and space science has continued to develop [1, 2]. Among them, space technology refers to the comprehensive engineering technology that provides technical means and guarantee conditions for space activities. Space application refers to the use of space technology and space resources developed in the fields of scientific research, national economy, national defense construction, culture and education. Space resources refer to various environmental, energy and material resources available for human development and utilization outside the Earth's atmosphere, as well as material resources of celestial bodies such as high space position, high vacuum, ultra-low temperature, strong radiation, microgravity environment and solar energy outside the earth [3,4,5]. As space activities become more competitive, the new space systems requirements such as increased functionality and reduced volume make the need for advanced microelectronic devices even more urgent.

The core hardware chip of electronic equipment is completed with fundamental transistors after a variety of processes to realize multiple functions [6,7,8]. In order to meet the demand, it is necessary to reduce the feature size of transistors to improve the performance of the chips. When designing chips, it is common to integrate devices and circuits into the smallest possible area in order to produce cheaper, smaller, and faster electronic devices. With the continuous progress of the chip manufacturing process, the chip can be smaller and smaller, while becoming more powerful. But traditional Si device feature sizes have reached their limits. The size of the chip will also bring some problems, such as: increased production costs: if the size of the chip becomes larger, more materials are needed, and more manufacturing steps are required, which will increase the production cost. Heat dissipation problems: As the size increases, the heat generated by the chip will also increase, requiring a more powerful cooling system to cool the chip, which will make the device bulkier. Reduced integration: If devices and circuits are dispersed over a larger area, interference and signal loss between circuits will increase, affecting the performance and stability of the chip [9,10,11,12,13].

Therefore, in order to further improve device performance, it is necessary to find alternative materials for silicon or develop new principal devices. Among them, two-dimensional (2D) materials are candidates for a new generation because of their atomic thickness. In a wide variety of 2D materials, black phosphorus (BP) has excellent physical properties such as in-plane anisotropy, thickness-dependent direct band gap and high carrier mobility. Recent experiments have shown that few layer BP can be obtained by mechanical exfoliation for next-generation electronic and optical applications [14,

2 Methods

The BP bulks used in our article were purchased from Dutch HQ Graphene company through the dealer. A small number of BP flakes are stripped from the bulk crystal and then transferred to a heavily doped silicon substrate covered with a 300 nm SiO2 layer by using mechanical strip** method to place the BP on the substrate. Subsequently, source/drain metal contacts are formed by electron beam lithography (EBL) and a 20 nm/50 nm thick Cr/Au metal deposition and lift-off processes. The completed BP FET device was first electrically measured using the Keithley 4200 semiconductor parameter analyzer in a vacuum atmosphere. The measured samples were treated with N2 plasma with different power and duration. After treatment, BP FETs were again electrically characterized under vacuum conditions.

The schematic diagram and optical micrograph of a BP FET with channel length of 2 μm are shown in Fig. 1a, b, respectively. On a 300nm silicon dioxide sheet, the two-dimensional material will appear different colors depending on the thickness. By empirically determining the thickness represented by the color, a thinner material can be selected as the channel material of the device. Here, BP is generally selected with a thickness of about 10 nm. Because the BP device will be briefly exposed to the air during the N2 plasma treatment. 10 nm black phosphorus can ensure the normal operation of the device during the whole experiment. Figure 1c, d are scanning electron microscope (SEM) images of BP devices. In SEM images, 2D materials and electrodes can be clearly seen. The device presents very clean channels and electrodes at large magnification.

Fig. 1
figure 1

a The schematic diagram of the device structure. b The optical microscope image of the BP FET. c SEM images of the BP FET. d The SEM image magnification

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3 Results and discussion

A clear characteristic of p-type transistor behavior can be seen in the transfer characteristics of the few layers BP FET, as shown by the black line in Fig. 2. The value of Vd in Fig. 2 is − 1 V. Before N2 plasma processing, the six typical devices are chosen to shown in Fig. 2, which exhibits typical p-type transistor behavior. The prepared devices were divided into three groups and treated with 10W, 20W and 30W plasma, respectively. The N2 plasma treatment duration is set to 30 s. After processing, the device still maintains p-type characteristics. However, the performance of the BP FETs after N2 plasma treatment is not fixed. When the N2 plasma power is 10W and 30W, the conduction current of the device is unstable, and the off-state current is not consistent. The performance of the device varies inconsistently after 10W and 30W plasma treatment. However, when the processing power is 20W, the on-state current (Ion) and off-state current (Ioff) increase significantly. The on/off ratio is reduced. Figure 2 shows the typical characteristics of the devices after different power treatment.

Fig. 2
figure 2

a-b The transfer curves of the BP FET without and with 10W N2 plasma treatment for 30s. c-d The transfer curves of the BP FET without and with 20W N2 plasma treatment for 30s. e–f The transfer curves of the BP FET without and with 30W N2 plasma treatment for 30s

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In order to observe the effect of plasma power on the performance of the device more clearly, the electrical characteristic parameters of several devices are extracted. One of the more important applications of FET in logic circuits is current switching, which is turned on or off by gate voltage control devices. Then the current ratio of the device in the on state and the off state is the switching ratio, that is, Ion/Ioff. When the device is in the on state, the size of the leakage current is the on-state current Ion, which will affect the running speed of the device. When the device is in the off state, the leakage current is the off state current Ioff, and the off-state current will affect the power consumption of the device. The transistor can be regarded as a faucet, then the switch ratio is equivalent to the water flow ratio of the water and the water off, the greater the water flow, the higher the efficiency of the faucet, the smaller the water flow, the less waste, the faucet has played a role in turning off. If the faucet is turned off, there is still water drip** continuously, then the quality of the faucet is not good at this time and needs to be replaced. The larger the switch ratio in logic device, the better the device performance.

For the convenience of comparison, the device performance change rates of 15 devices are given in Fig. 3.

Fig. 3
figure 3

a The change of on-state current ratio with power before and after N2 plasma treatment. b The change of off-state current ratio with power before and after N2 plasma treatment. c The change of on/off current ratio with power before and after N2 plasma treatment. d The change of mobility ratio with power before and after N2 plasma treatment

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In Fig. 3a, the ratio of the on-state current of the black phosphorus transistor after treatment and before treatment is taken as the vertical axis for ease of comparison. It can be clearly seen that the influence of 10W processing on the conduction current of the device is uncertain, while the open-state current of the device is reduced by 30W processing. Only the Ion of the 20W treated device is increased, and the increase factor is > 1.2.

Figure 3b shows the change of the ratio of the off-state current of the black phosphorus transistor with the processing power after treatment and before treatment. It is noted that 20W N2 plasma processing has the greatest influence on the off-state current of the device, which can reach up to 300 times of the original current. N2 plasma mainly affect the channel surface of black phosphorus devices, increasing surface defects and impurities. From our experimental results, the threshold of the device moves forward and the p terminal current increases, indicating that the device is indeed p-doped. Thus, N ions are also inserted into the BP lattice to form p-type do** of the channel [39, 40]. However, the conductive channel of the BP FET is mainly at the lower interface. When the power is small, the change of the channel surface has a little effect on the conduction channel at the lower interface, which results in erratic performance changes. As the power increases to 20W, the interface defects increase, and the do** of N ions also increases. Thus, the p-type do** effect of current increases obviously and consistently. When the power is further increased to 30W, the plasma damages the channel lattice of the device, and the damage of the channel material leads to the performance attenuation of the device.

In Fig. 3c, the switching ratio of the device after 30W treatment is significantly smaller than that of the other two, indicating that the performance of the device is indeed attenuated due to material damage.

Figure 3d shows the change of the field effect mobility of the device after treatment, in which the mobility of the 10W treatment has the largest fluctuation range, indicating that the treatment effect is unstable. With the increase of power, the variation range of mobility decreases and the treatment effect becomes more consistent. The field-effect mobility (μ) of the device can be calculated by the following formula:

$$\mu =\frac{1}{{C}_{i}}{g}_{m}\frac{L}{W}\frac{1}{{V}_{d}}$$
(1)

where gm is transconductance, which defined as gm = d(Id)/d(Vg), L is the channel length, W is the channel width, Ci is the capacitance of the back gate, and Vd is the source and drain bias. Mobility is used to characterize the average drift velocity of carriers in a semiconductor under the action of a unit electric field. For a practical device, mobility is an important performance consideration. Similar to the water discharge speed of a faucet, under the same water pressure per unit area per unit time, the more and faster the water is discharged, the more efficient and useful it will be in line with our definition. Then, for a high-performance electronic device, the faster the carrier drift speed, the faster the device runs, the better the performance. FET as the basic unit operation speed increase, the entire integrated circuit to the chip to the electronic products of the computing and processing information ability will be accelerated, the higher the efficiency of electronic products, the better the product performance, the more to meet the needs of the market. Among them, the ratio of the 30W N2 plasma treatment approaches 1, which indicating that the improvement is not undesirability. Overall consideration, 20W N2 plasma treatment is the best one.

In order to further investigate the effect of processing time on device performance, we chose to use 20W N2 plasma to process the same device multiple times. The cumulative duration is used as the total duration.

In Fig. 4a, the transfer characteristic curves of BP FET treated with different time periods were compared. It can be obviously seen that the on-state current and off-state current of the device increase with the increase of the time, but the device characteristics after treatment are significantly reduced when the time exceeds 50 s, indicating that the processing time of 70 s has damage to the device. When the N2 plasma duration is suitable, the treatment will improve the performance of the devices. When the treatment duration exceeds a certain limit, the material will be damaged and the performance will be reduced.

Fig. 4
figure 4

a The transfer curves of the BP FET with 20W N2 plasma treatment for 0s, 10s, 30s, 50s, and 70s, respectively. The output characteristic curves of the BP FET with 20W N2 plasma treatment for 0s (b), 10s (c), 30s (d), 50s (e), and 70s (f), respectively

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Figure 4b–f shows the corresponding output characteristic curves of the devices processed for different duration. The value of Vg in the output characteristics is from 0 V, − 10 V, − 20 V, − 30 V, − 40 V and − 50 V, respectively. It is obvious that the off-state current of the devices after processing is relatively large. The maximum current first increases with the increase of the processing time, and then decreases with the increase of the processing time after more than 50 s.

Table 1 is the summary of the characteristics of recent BP transistors. BP has excellent physical properties. Since the intrinsic properties of black phosphorus depend on black phosphorus materials, the basic properties of different produced materials are inconsistent. Thus, we mainly discuss a change comparison of our devices before and after processing to highlight the role of N2 plasma. As shown in the Table 1, the performance of our work is in the normal range in recent studies. Our devices range in mobility from 31 to 304 cm2/V·s.

Table 1 Summary of characteristics of recent BP transistors
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4 Conclusion

In summary, in order to meet the high-performance requirements of electronic devices for the implementation of new space systems, we explored N2 plasma treatment to regulate the performance of BP FET devices. N2 plasma can effectively improve the on-state current and mobility of the device. Better do** techniques are essential to further improve the transport performance of materials, including BP. It lays the hardware foundation for the application of subsequent devices in aerospace technology and space informatics.