15 Result(s)
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Chapter
Franco Fummi
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Chapter and Conference Paper
Toward Smart Doors: A Position Paper
Conventional automatic doors cannot distinguish between people wishing to pass through the door and people passing by the door, so they often open unnecessarily. This leads to the need to adopt new systems in ...
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Chapter and Conference Paper
On the Simulation and Automatic Parametrization of Metabolic Networks Through Electronic Design Automation
This work presents a platform for the modelling, simulation and automatic parametrization of semi-quantitative metabolic networks. Starting from a network modelled through Petri Nets (PN) and represented in SB...
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Chapter
Generation of Functional Mockup Units for Transactional Cyber-Physical Virtual Platforms
Modeling Cyber-Physical Systems requires aggregating semantics and languages tailored to different specific domains, while simulating these systems requires integrating different tools and technologies. Academ...
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Chapter
Fault Analysis in Analog Circuits Through Language Manipulation and Abstraction
Each year automotive systems are becoming smarter thanks to their enhancement with sensing, actuation and computation features. The recent advancements in the field of autonomous driving have increased even mo...
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Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces
Verification of cyber-physical systems SW often requires simulation of accurate heterogeneous HW models. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simu...
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Chapter
Smart System Case Studies
This chapter presents two case studies showing how the proposed approach applies to smart system design and optimization. The former is the virtual prototy** platform built for a laser pico-projector actuato...
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Chapter
Design Domains and Abstraction Levels for Effective Smart System Simulation
Smart systems represent a broad class of systems defined as intelligent, miniaturized devices incorporating functionality like sensing, actuation, and control. In order to support these functions, they must in...
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Chapter
Code Generation Alternatives to Reduce Heterogeneous Embedded Systems to Homogeneity
The high level of heterogeneity of modern embedded systems forces designers to use different computational models and formalisms, thus making reuse and integration very difficult tasks. Reducing such an hetero...
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Chapter and Conference Paper
Dynamic Modeling and Simulation of Leukocyte Integrin Activation through an Electronic Design Automation Framework
Model development and analysis of biological systems is recognized as a key requirement for integrating in-vitro and in-vivo experimental data. In-silico simulations of a biochemical model allows one to test d...
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Chapter
SystemC Simulation of Networked Embedded Systems
The design and simulation of next-generation networked embedded systems are a challenging task since System design choices may affect the network behavior and Network design choices may impact on the System de...
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Chapter and Conference Paper
Hardware Design and Simulation for Verification
The development of more and more complex embedded systems constitutes a very challenging task for EDA experts, due to their HW/SW-mixed nature joint to the high demand for quality and reliability. Recently, bo...
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Chapter
LAERTE++: An Object Oriented High-Level TPG for SystemC Designs
This paper describes Laerte++, a high-level test pattern generator (TPG) for SystemC designs. All necessary features of a high-level TPG (e.g., fault models definition, hierarchical analysis, coverage measurem...
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Chapter
SystemC as a Complete Design and Validation Environment
Synthesis tools for SystemC descriptions are mature enough to cover the design flow from the system level to the gate level, whilst SystemC centered validation methodologies are still under development. This c...
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Chapter
Functional Test Generation
Functional testing is a common methodology for a quick verification of the cor‑rect implementation of a design. Moreover, functional testing allows to higher the level of abstraction at which test pattern gene...
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Chapter
Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement
A methodology for modifying VHDL descriptions is the core of this paper. Modifications are performed on general RTL descriptions composed of a mix of control and computation, that is, the typical type of descr...
