20 Result(s)
within
Antonio Mastrandrea
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Chapter and Conference Paper
Measurements of Exhaled CO2 Through a Novel Telemedicine Tool
This paper proposes a telemedicine tool (complete of hardware, software and 3D printed face mask) for analyzing exhaled carbon dioxide (CO2) levels. Our interest in CO2 pattern is due to its correlation to psycho...
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Chapter and Conference Paper
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach
Efficient and cost-effective functional verification strategies are more and more essential in digital integrated system design. This paper presents a low-cost approach to meet this challenge, introducing a un...
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Chapter and Conference Paper
Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects
Among all the fault tolerance (FT) techniques developed over the years, Dual-core lock-step techniques have emerged as an effective approach to enhance the fault tolerance capabilities of these systems. Howeve...
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Chapter and Conference Paper
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design
The miniaturization of electronic devices and the improved operating speeds increase the likelihood of single event faults. Differently from Single Event Upset (SEU) faults, Single Event Transient (SET) faults...
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Chapter and Conference Paper
Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy
Dual-core lock-step techniques have emerged as an effective approach to enhance the fault tolerance (FT) capabilities of many safety-critical and mission-critical systems [3, 5], since the probability of faults i...
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Chapter and Conference Paper
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor
Using Artificial Intelligence (AI) techniques has become the best solution in many applications
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Chapter and Conference Paper
Improving SET Fault Resilience by Exploiting Buffered DMR Microarchitecture
Over the past years, several complex redundant systems capable of executing safety applications were developed, with the common purpose of protecting circuits against Single Event Upset (SEU) in sequential log...
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Chapter and Conference Paper
3D-Printed Face Mask with Integrated Sensors as Protective and Monitoring Tool
The outbreak of the recent Covid-19 pandemic changed many aspects of our daily life, such as the constant wearing of face masks as protection from virus transmission risks. Furthermore, it exposed the healthca...
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Chapter and Conference Paper
A Ladder Network Theoretical Approach for the Automatic Monitoring of Distributed Sensors
Ladder networks are typically used for passive filters, and they also represent a good equivalent model for mechanical, chemical and thermal system. These networks could be also used in the study of sensor net...
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Chapter and Conference Paper
Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators
Reconfigurable processing cores for IoT and edge computing applications are emerging topics to calibrate costs, energy consumption and area occupation with performance and reliability on Commercial Off the She...
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Chapter and Conference Paper
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer
The electronics devices that operate in the extreme space environment require a high grade of reliability in order to mitigate the effect of the ionizing particles. For COTS components this can be achieved usi...
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Chapter and Conference Paper
Quality Aware Selective ECC for Approximate DRAM
DRAMs are DRAM memories where energy saving techniques have been implemented by trading off bit-cell error rate with power consumption. They are considered part of the building blocks in the larger ar...
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Chapter and Conference Paper
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor
Interleaved multi-threaded architectures (IMT) have proven to be an advantageous solution to maximize the pipeline utilization, when it comes to executing parallel applications, as different threads operate di...
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Chapter and Conference Paper
On the Simulation and Automatic Parametrization of Metabolic Networks Through Electronic Design Automation
This work presents a platform for the modelling, simulation and automatic parametrization of semi-quantitative metabolic networks. Starting from a network modelled through Petri Nets (PN) and represented in SB...
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Chapter and Conference Paper
Approximate Memory Support for Linux Early Allocators in ARM Architectures
Approximate computing a new paradigm for energy efficient design, based on the idea of designing digital systems that trade off accuracy for energy consumption. The paradigm can be applied different unit...
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Chapter and Conference Paper
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes
Internet-of-Things end-nodes demand low power processing platforms characterized by heterogeneous dedicated units, controlled by a processor core running multiple control threads. Such architecture scheme fits...
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Chapter and Conference Paper
Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing
This paper presents the and the implementation of fully combinatorial floating point unit (FPU). The FPU can be reconfigured at implementation time order to use an arbitrary number of bits for the mantis...
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Chapter and Conference Paper
Geometry Scaling Impact on Leakage Currents in FinFET Standard Cells Based on a Logic-Level Leakage Estimation Technique
Static power consumption is one of the most critical issues in CMOS digital circuits, and FinFET technology is being recognized as a valid solution for the problem. In this chapter, we utilize a logic-level le...
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Chapter and Conference Paper
An Emulator for Approximate Memory Platforms Based on QEmu
In this paper, an emulation environment for approximate memory architectures is presented. In the context of error tolerant applications, in which energy is saved at the expense of the occurrence of errors in ...
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Chapter and Conference Paper
Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder
This paper describes the analysis, in terms of tolerance to errors on data, of a H.264 software video encoder; proposes a strategy to select data structures for approximate memory allocation and reports the im...
