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Chapter
High Level Synthesis in the THEDA System
Starting with a behavioral description of a digital system along with a set of time and/or resource constraints, the goal of a silicon compiler[1][2] is to produce a structure or even a layout of the system. O...
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Chapter
Gate Sizing for Cell-Based Designs
Without changing to its topology, a logic circuit can be optimized for area, speed or both by sizing its gates. In this chapter, we describe an approach to the gate sizing problem in cell-based logic designs. ...
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Chapter
A SOC Controller for Digital Still Camera
We present our experience of designing a single-chip multimedia SOC for advanced digital still camera from specification all the way to mass production. The process involves collaboration with camera system de...
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Chapter
Essential Issues In System-On-A-Chip Design
Due to advance in semiconductor manufacturing technology, integration of whole electronics system on a single chip is feasible. Starting with baseline CMOS logic, semiconductor wafer manufacturers have gradual...
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Book
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Book
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Book
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Book
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Chapter and Conference Paper
HarDNet-BTS: A Harmonic Shortcut Network for Brain Tumor Segmentation
Tumor segmentation of brain MRI image is an important and challenging computer vision task. With well-curated multi-institutional multi-parametric MRI (mpMRI) data, the RSNA-ASNR-MICCAI Brain Tumor Segmentatio...
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Chapter and Conference Paper
HarDNet-DFUS: Enhancing Backbone and Decoder of HarDNet-MSEG for Diabetic Foot Ulcer Image Segmentation
Diabetic foot ulcers are caused by neuropathic and vascular complications of diabetes mellitus. In order to provide a proper diagnosis and treatment, wound care professionals need to extract accurate morpholog...
