Abstract
Without changing to its topology, a logic circuit can be optimized for area, speed or both by sizing its gates. In this chapter, we describe an approach to the gate sizing problem in cell-based logic designs. Our algorithm picks from the cell library one out of several functionally-identical cells for every gate of a combinational Boolean logic circuit so that the circuit delay meets a user-specified constraint while the total gate size is minimized. Specifically, we deal with the relationship between the delays of a set of paths and the total size of the constituent gates of the path set. We also describe a fine-step sizing strategy that enables the sizer to treat all paths fairly. A software system called Theda.CBS (Tsing Hua Electronic Design Automation — Cell-Based Sizing) has been implemented. We have tested Theda.CBS on a set of benchmark circuits targeting towards different cell libraries. A series of experiments have been conducted to investigate the effectiveness of the algorithm.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
R. Brayton et al., “MIS: A Multiple-Level Logic Optimization System,” IEEE Transactions on CAD of ICS, Vol. 6, No. 11, pp. 1062–1081, November 1987.
P. K. Chan, “Algorithms for Library-Specific Sizing of Combinational Logic,” 27th ACM/IEEE Design Automation Conference, pp. 353–356, June 1990.
M-C. Chang and C-F. Chen, “PROMPT3 — A Cell-Based Transistor Sizing Program Using Heuristic and Simulated Annealing Algorithms,” IEEE 1989 Custom Integrated Circuits Conference, pp. 17.2.1–17.2.4., May 1989.
H. Y. Chen and S. M. Kang, “iCOACH: A Circuit Optimization Aid for CMOS High-performance Circuits,” International Conference on Computer-Aided Design, pp. 372–375, November 1988.
H. Y. Chen and S. M. Kang, “A New Circuit Optimization Technique for High Performance CMOS Circuits,” IEEE Transactions on CAD of ICS, Vol. 10, No. 5, pp. 670–676, May 1991.
Z-J. Dai and K. Asada, “MOSIZ: A Two-step Transistor Sizing Algorithm Based on Optimal Timing Assignment Method for Multi-stage Complex Gates,” IEEE 1989 Custom Integrated Circuits Conference, pp. 17.3.1–17.3.4, May 1989.
D. H. Du, S. H. Yen, and H. Ghanta, “Efficient Algorithms for Extracting the k-Most Critical Paths in Timing Analysis,” Journal of Computer-Aided VLSI Design, pp. 191–215, March 1991.
J. P. Fishburn and A. E. Dunlop, “TILOS: A Posynomial Programming Approach to Transistor Sizing,” International Conference on Computer-Aided Design, pp. 326–328, November 1985.
T. Gao, P. M. Vaidya, and C. L. Liu, “A New Performance Driven Placement Algorithm,” International Conference on Computer-Aided Design, pp. 44–47, November 1991.
L. S. Hensler and W. Fichtner, “Transistor Sizing for Large Combinational Digital CMOS Circuits,” INTEGRATION, the VLSI Journal, Vol. 10, pp. 155–168, 1991.
Hua-Lon Microelectronics Co., “Hua-Lon 1.2 t CMOS Cell Library Data Book,” Hsin-Chu Taiwan, 1991.
S. Lin, M. Marek-Sadowska and E. Kuh, “Delay and Area Optimization in Standard Cell Design,” 27th ACM/IEEE Design Automation Conference, pp. 349–352, June 1990.
D. Marple, “Transistor Size Optimization in the Tailor Layout System,” 26th ACM/IEEE Design Automation Conference, pp. 43–48, June 1989.
S. S. Sapatnekar and V. B. Rao, “IDEAS: A Delay Estimator and Transistor Sizing Tool for CMOS Circuits,” IEEE 1990 Custom Integrated Circuits Conference, pp. 9.3.1 — 9.3.4, May 1990.
S. Sutanthavibul and E. Shragowitz, “Dynamic Prediction of Critical Paths And Nets For Constructive Timing-Driven Placement,” 28th ACM/IEEE Design Automation Conference, pp. 632–635, June 1991.
J-M. Shyu, A. Sangiovanni-Vincentelli, J. P. Fishburn and A. E. Dunlop, “Optimization-Based Transistor Sizing,” IEEE Journal of Solid-State Circuits, Vol. 23, No. 2, pp. 400–409, April 1988.
H. Youssef, E. Shragowitz and L. C. Bening, “Critical Path Issue in VLSI Design,” International Conference on Computer-Aided Design, pp. 520–523, November 1989.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1993 Springer Science+Business Media New York
About this chapter
Cite this chapter
Lee, WP., Lin, YL. (1993). Gate Sizing for Cell-Based Designs. In: Sasao, T. (eds) Logic Synthesis and Optimization. The Kluwer International Series in Engineering and Computer Science, vol 212. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3154-8_16
Download citation
DOI: https://doi.org/10.1007/978-1-4615-3154-8_16
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6381-1
Online ISBN: 978-1-4615-3154-8
eBook Packages: Springer Book Archive