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Book
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Chapter
Concluding Remarks
In the first part of this book, we introduced a state-of-the-art on-chip interconnection network design and some of the important design problems of NoC. Then, in the second part of this book, many important d...
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Chapter
Energy-Aware Application Map** for BiNoC
Power-efficient scheduling is investigated for BiNoC architecture in this chapter. To minimize the power consumption of real time applications on BiNoC, time slacks in a preliminary schedule are exploited to c...
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Chapter
Preliminaries
Network-on-Chip is the term used to describe an architecture that has maintained readily designable solutions in face of communication-centric trends. In this chapter, we will briefly review some concepts on t...
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Chapter
Fault Tolerance in BiNoC
For fault-tolerant data-link connections, a novel Bi-directional Fault-Tolerant NoC (BFT-NoC) scheme that supports both static and dynamic channel failures is proposed in this chapter. Except for a little perf...
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Chapter
Communication Centric Design
As the density of VLSI design increases, the complexity of each component in a system raises rapidly. To accommodate the increasing transistor density, higher operating frequencies, and shorter time-to-market ...
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Chapter
Techniques for High Performance Noc Routing
In an NoC, designing an efficient routing mechanism is critical to the performance. One crucial issue in the routing strategies is, under the premise of deadlock and livelock freedoms, how to enhance routing a...
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Chapter
Quality-of-Service in BiNoc
A QoS-aware BiNoC architecture is proposed in this chapter to support guarantee-service (GS) traffic while reducing packet delivery latency. With the dynamically self-reconfigured bidirectional communication c...
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Chapter
Performance-Energy Tradeoffs for Noc Reliability
The NoC architecture promises reliable high performance low power on-chip communication. To realize such promises, performance-energy trade-off analysis is carried out in this chapter to compare two competing ...
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Chapter
Bidirectional Noc Architecture
A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed in this chapter to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows itself to be dynamica...
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Chapter
Energy-Aware Task Scheduling for Noc-Based DVS System
For real time applications, time slacks of a preliminary task schedule may be exploited to conserve energy. This can be accomplished by leveraging the dynamic voltage scaling (DVS) technique to slow down clock...
