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Chapter and Conference Paper
Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core
Development of analog electronics solutions for space avionics is expensive and time-consuming. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog d...
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Chapter and Conference Paper
Adaptive and Evolvable Analog Electronics for Space Applications
Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers...
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Chapter and Conference Paper
Transistor-Level Circuit Experiments Using Evolvable Hardware
The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been ...
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Chapter and Conference Paper
Speed Enhancement with Soft Computing Hardware
During the past few years JPL has been actively involved in soft computing research encompassing theory, architecture, and electronic hardware. There are a host of soft computing applications that require orde...
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Chapter and Conference Paper
Cascade error projection: A learning algorithm for hardware implementation
In this paper, we workout a detailed mathematical analysis for a new learning algorithm termed Cascade Error Projection (CEP) and a general learning frame work. This frame work can be used to obtain the cascad...
