Abstract
During the past few years JPL has been actively involved in soft computing research encompassing theory, architecture, and electronic hardware. There are a host of soft computing applications that require orders of magnitude enhancement in speed compared to present day simulations on digital machines. For real-time computing this is made possible by selecting suitable algorithms, designing compatible architectures and implementing them in parallel processing hardware. A compact low-power hardware design for insitu applications uses a 3D-packaged artificial neural network (ANN) multichip module performing object classification and recognition with 1012 multiply-sum operations per second (ops). Additionally, development on evolvable hardware (EHW) implemented on reconfigurable electronic hardware has shown exciting high-speed evolution of various digital and analog circuits. We review our work to demonstrate real-time processing.
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References
Duong, TA, Daud T, Thakoor AP (1995) United States Patent #5479579, Cascaded VLSI neural network architecture for on-line learning.
Stoica A, Keymeulen D, Tawel R, Lazaro C, Li W-T (1999) Evolutionary experiments with a fine-grained reconfigurable architecture for analog and digital CMOS circuits. In Stoica A, Keymeulen D, Lohn J (eds) Proc. First NASA/DOD Workshop on Evolvable Hardware, IEEE Computer Society Press, pp. 77–84.
Udomkesmalee S, Thakoor A, Padgett C, Daud T, Fang W-C, Suddarth SC (1997) VIGILANTE: An advanced sensing/processing testbed for ATR applications. In Sadjadi FA (ed) Proc. SPIE Conf. Automatic Target Recognition VII vol. 3069, pp. 82–93.
Howard A, Padgett C (1999) Real time intelligent target detection and analysis with machine vision In Computational Intelligence: Methods and Applications (CIMA).
Howard A, Padgett C, Brown K (1999) Intelligent target detection in hyperspectral imagery In Proceedings of the Thirteenth International Conference on Applied Geologic Remote Sensing.
Howard A, Padgett C (2000) A generalized approach to real-time pattern recognition in sensed data. In Pattern Recognition.
Stoica A, Zebulum R, Keymeulen D, Tawel R, Daud T, Thakoor A (2001), Reconfigurable VLSI Architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips. In IEEE Transactions on VLSI Systems, Special Issue on Reconfigurable and Adaptive VLSI Systems, vol 9, pp. 227–232.
Ferguson MI, Stoica A, Zebulum R, Keymeulen D, Duong V (2002) An evolvable hardware platform based on DSP and FPTA. In AAAI/Proceedings of the Genetic and Evolutionary Computation Conference–Late Breaking Papers, New York, NY, pp 145–152.
Zebulum RS, Stoica A, Keymeulen D, Ferguson MI, Duong V, Guo X, Vorperian V (2003), Automatic evolution of tunable filters using SABLES. In Tyrrell AM, Haddow PC, Torresen J (eds) 5th International Conference Evolvable Systems: From Biology to Hardware, Springer, pp 286–295.
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Daud, T. et al. (2003). Speed Enhancement with Soft Computing Hardware. In: Kaynak, O., Alpaydin, E., Oja, E., Xu, L. (eds) Artificial Neural Networks and Neural Information Processing — ICANN/ICONIP 2003. ICANN ICONIP 2003 2003. Lecture Notes in Computer Science, vol 2714. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44989-2_125
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DOI: https://doi.org/10.1007/3-540-44989-2_125
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