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Chapter and Conference Paper
A Power-Efficient and Scalable Load-Store Queue Design
The load-store queue (LQ-SQ) of modern superscalar processors is responsible for kee** the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the cap...
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Chapter and Conference Paper
Wavelet Transform for Large Scale Image Processing on Modern Microprocessors
In this paper we discuss several issues relevant to the vectorization of a 2-D Discrete Wavelet Transform on current microprocessors. Our research is based on previous studies about the efficient exploitation ...
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Chapter and Conference Paper
2-D Wavelet Transform Enhancement on General- Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation
This paper addresses the implementation of a 2-D Discrete Wavelet Transform on general-purpose microprocessors, focusing on both memory hierarchy and SIMD parallelization issues. Both topics are somewhat relat...