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Chapter and Conference Paper
Towards a Malleable Tensorflow Implementation
The TensorFlow framework was designed since its inception to provide multi-thread capabilities, extended with hardware accelerator support to leverage the potential of modern architectures. The amount of paral...
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Article
A power measurement environment for PCIe accelerators
We describe and validate a complete hardware/software environment for power consumption analysis of PCIe-based accelerators, using the Intel Xeon Phi co-processor as the target platform. Our environment is fle...
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Chapter and Conference Paper
Accelerating Data Race Detection with Minimal Hardware Support
We propose a high performance hybrid hardware/software solution to race detection that uses minimal hardware support. This hardware extension consists of a single extra instruction, StateChk, that simply retur...
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Chapter and Conference Paper
Topic 4: High Performance Architectures and Compilers
This topic deals with architecture design and compilation for high performance systems – the discovery and support of parallelism at all levels. The areas of interest range from microprocessors to large-scale ...
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Chapter and Conference Paper
Wavelet Transform for Large Scale Image Processing on Modern Microprocessors
In this paper we discuss several issues relevant to the vectorization of a 2-D Discrete Wavelet Transform on current microprocessors. Our research is based on previous studies about the efficient exploitation ...
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Chapter and Conference Paper
2-D Wavelet Transform Enhancement on General- Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation
This paper addresses the implementation of a 2-D Discrete Wavelet Transform on general-purpose microprocessors, focusing on both memory hierarchy and SIMD parallelization issues. Both topics are somewhat relat...
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Chapter and Conference Paper
Value Prediction as a Cost-Effective Solution to Improve Embedded Processors Performance
The growing market of embedded systems and applications has led to the making of more general embedded processors, with some features traditionally associated with general-purpose microprocessors. Following th...
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Chapter and Conference Paper
Implementation of Hybrid Context Based Value Predictors Using Value Sequence Classification
Value prediction is as yet a very novel technique, whose efficiency has still to be proved. To take advantage of this emerging technique in the short term it is essential to design accurate and low cost value ...
