5 Result(s)
within
Daniel Chaver
English
-
Chapter and Conference Paper
An OS-Oriented Performance Monitoring Tool for Multicore Systems
Hardware performance monitoring counters (PMCs) have proven effective in characterizing application performance. Because PMCs can be only accessed directly at the OS privilege level, kernel-level tools must be...
-
Chapter and Conference Paper
Exploring the Throughput-Fairness Trade-off on Asymmetric Multicore Systems
Symmetric-ISA (instruction set architecture) asymmetric-performance multicore processors (AMPs) were shown to deliver higher performance per watt and area than symmetric CMPs (Chip Multi-Processors). Previous ...
-
Chapter and Conference Paper
A Power-Efficient and Scalable Load-Store Queue Design
The load-store queue (LQ-SQ) of modern superscalar processors is responsible for kee** the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the cap...
-
Chapter and Conference Paper
Wavelet Transform for Large Scale Image Processing on Modern Microprocessors
In this paper we discuss several issues relevant to the vectorization of a 2-D Discrete Wavelet Transform on current microprocessors. Our research is based on previous studies about the efficient exploitation ...
-
Chapter and Conference Paper
2-D Wavelet Transform Enhancement on General- Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation
This paper addresses the implementation of a 2-D Discrete Wavelet Transform on general-purpose microprocessors, focusing on both memory hierarchy and SIMD parallelization issues. Both topics are somewhat relat...
