31 Result(s)
within
English
Engineering
Image Processing and Computer Vision
Pattern Recognition
Ben Ep**er
Article
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Article
Fast multiplier bit-product matrix reduction using bit-ordering and parity generation
The “Wallace Tree/Dadda Fast Multiplier” consists of the following three steps: 1) form a bit-product matrix; 2) reduce the bit-product matrix to two rows; and 3) sum the two rows. This article describes a nov...
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Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter
Designing embedded systems is a challenging task during which wrong choices can lead to extremely costly re-design loops, especially when these wrong choices are made during the algorithm specification and the...
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Edge-based Segmentation Using Robust Evolutionary Algorithm Applied to Medical Images
Although medical image segmentation is a hard task in image processing, it is possible to reduce its complexity by considering it as an optimization problem. This paper presents a robust evolutionary algorithm...
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Open AccessLeakage-Aware Multiprocessor Scheduling
When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however, static power consumption du...
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Open AccessInstruction-Level Fault Tolerance Configurability
Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance (FT) is becoming increasingly important in computing systems. Several schemes have been proposed to en...
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Open AccessParallel Scalability of Video Decoders
An important question is whether emerging and future applications exhibit sufficient parallelism, in particular thread-level parallelism, to exploit the large numbers of cores future chip multiprocessors (CMPs...
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Compiling for Reduced Bit-Width Queue Processors
Embedded systems are characterized by the requirement of demanding small memory footprint code. A popular architectural modification to improve code density in RISC embedded processors is to use a reduced bit-...
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Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis
A processor architecture combining high-performance and low-power is presented. A prototype chip, Xetal-II, has been realized in 90 nm CMOS technology based on the proposed architecture. Recent experimental re...
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Open AccessColor image segmentation using multi-level thresholding approach and data fusion techniques: application in the breast cancer cells images
In this article, we present a new color image segmentation method, based on multilevel thresholding and data fusion techniques which aim at combining different data sources associated to the same color image i...
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FPGA architecture of the LDPS Motion Estimation for H.264/AVC Video Coding
Motion estimation is a highly computational demanding operation during video compression process and significantly affects the output quality of an encoded sequence. Special hardware architectures are required...
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Implementation and Optimization of an Enhanced PWD Metric for H.264/AVC on a TMS320C64 DSP
A common method for selecting the best prediction mode based on block matching algorithm is to compare, for each source block, the associated distortions among the available prediction candidates. The human vi...
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Open AccessLBPV descriptors-based automatic ACR/BIRADS classification approach
Mammogram tissue density has been found to be a strong indicator for breast cancer risk. Efforts in computer vision of breast parenchymal pattern have been made in order to improve the diagnostic accuracy by r...
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Parallel HEVC Decoding on Multi- and Many-core Architectures
The Joint Collaborative Team on Video Decoding is develo** a new standard named High Efficiency Video Coding (HEVC) that aims at reducing the bitrate of H.264/AVC by another 50 %. In order to fulfill the com...
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A Very High Throughput Deblocking Filter for H.264/AVC
This paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filt...
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A Finite Volume Framework for Geometric Surface Processing
We present a surface denoising method using the vertex-centered finite volume method coupled with the mesh covariance fractional anisotropy. The approach is computationally fast and able to effectively remove ...
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Selection of a Closed-Form Expression Polynomial Orthogonal Basis for Robust Nonlinear System Identification
Polynomial nonlinear system identification suffers from numerical instability related to the ill-conditioning of the involved matrices. Orthogonal methods consist in conditioning the input signal in order to r...
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Instrumentation-Driven Validation of Dataflow Applications
Dataflow modeling offers a myriad of tools for designing and optimizing signal processing systems. A designer is able to take advantage of dataflow properties to effectively tune the system in connection with ...
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Open AccessSequential Monte Carlo filter based on multiple strategies for a scene specialization classifier
Transfer learning approaches have shown interesting results by using knowledge from source domains to learn a specialized classifier/detector for a target domain containing unlabeled data or only a few labeled...
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Embedded Real-Time H264/AVC High Definition Video Encoder on TI’s KeyStone Multicore DSP
To overcome high computational complexity of advanced video encoders for emerging applications that require real-time processing, multicore technology can be one of the promising solutions to meet this constra...
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Open AccessErratum to: Sequential Monte Carlo filter based on multiple strategies for a scene specialization classifier
