25 Result(s)
within
Jean-Philippe Diguet
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Chapter and Conference Paper
Towards Real-Time Human Detection in Maritime Environment Using Embedded Deep Learning
Marine search and rescue missions necessitate a lot of effort and expenses. The use of technological advancements facilitates discovering and locating individuals and aids in the directing of rescuers and medi...
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Article
MIMO-OFDM LTE system based on a parallel IFFT/FFT on NoC-based FPGA
The growing demand for wireless devices capable of performing complex communication processes has imposed an urgent need for high-speed communication systems and advanced network processors. This paper propose...
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Article
Near-Optimal Covering Solution for USV Coastal Monitoring using PAES
This paper addresses a multi-objective optimization problem for marine monitoring using USV. The objectives are to cover the maximum area with the lowest energy cost while avoiding collisions. The problem is s...
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Article
The Impact of Cache and Dynamic Memory Management in Static Dataflow Applications
Dataflow is a parallel and generic model of computation that is agnostic of the underlying multi/many-core architecture executing it. State-of-the-art frameworks allow fast development of dataflow applications...
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Chapter and Conference Paper
Parallel IFFT/FFT for MIMO-OFDM LTE on NoC-Based FPGA
The evaluation of wireless communication systems over the last decades has led to a growing demand for more advanced high-speed communication systems. In this paper, we propose a hardware workflow developed fo...
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Article
A novel **linx-based architecture for 3D-graphics
Spreading the use of embedded electronic multimedia systems to a large audience has more than one requirement. In fact, it should be operating in extreme conditions: random fluctuation conditions of network tr...
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Chapter and Conference Paper
Integrating Operators’ Preferences into Decisions of Unmanned Aerial Vehicles: Multi-layer Decision Engine and Incremental Preference Elicitation
Due to the nature of autonomous Unmanned Aerial Vehicles (UAV) missions, it is important that the decisions of a UAV stay consistent with the priorities of an operator, while at the same time allowing them to ...
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Article
Open AccessDynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding
The multiplication of connected devices goes along with a large variety of applications and traffic types needing diverse requirements. Accompanying this connectivity evolution, the last years have seen consid...
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Article
Move Based Algorithm for Runtime Map** of Dataflow Actors on Heterogeneous MPSoCs
Considering the evolution towards highly variable data flow applications based on an increasing impact of dynamic actors, we must target at runtime the best matching between dataflow graphs and heterogeneous m...
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Article
Open AccessDedicated object processor for mobile augmented reality - sailor assistance case study
This paper addresses the design of embedded systems for outdoor augmented reality (AR) applications integrated to see-through glasses. The set of tasks includes object positioning, graphic computation, as well...
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Chapter and Conference Paper
Discrete Control-Based Design of Adaptive and Autonomic Computing Systems
This invited paper makes an overview of our works addressing discrete control-based design of adaptive and reconfigurable computing systems, also called autonomic computing. They are characterized by their abi...
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Chapter and Conference Paper
Synchronization of Models of Rich Languages with Triple Graph Grammars: An Experience Report
We report our experience of using Triple Graph Grammars (TGG) to synchronize models of the rich and complex Architecture Analysis and Design Language (AADL), an aerospace standard of the Society of Automotive ...
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Chapter and Conference Paper
Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA
Our contribution lies in offering a fast and parametrized domain-space exploration to the designer, whose expertise drives the whole process while staying the actor of added-value creation. In this paper, we p...
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Article
A contribution to the reduction of the dynamic power dissipation in the turbo decoder
In the field of mobile communication systems, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper presents a contribution to the reduction of the powe...
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Chapter
End-to-End Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems
This chapter presents an end-to-end hierarchy of bitstreams repository for FPGA-based networked and partially reconfigurable systems. This approach targets embedded systems with very scare hardware resources t...
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Chapter
AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies
The ÆTHER project has laid the foundation of a complete new framework for designing and programming computing resources that live in changing environments and need to re-configure their objectives in a dynami...
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Chapter and Conference Paper
MPSoC Architecture-Aware Automatic NoC Topology Design
This paper presents a methodology for the automatic definition of NoC topology according to application and architecture requirements. The proposed solution, which has been implemented as a new step of our NoC...
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Chapter and Conference Paper
Ultra-Fast Downloading of Partial Bitstreams through Ethernet
In this paper we present a partial bitstreams ultra-fast downloading process through a standard Ethernet network. These Virtex-based and partially reconfigurable systems use a specific data-link level protocol...
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Chapter
Power and Energy Estimations in Model-Based Design
The aim of our works is to provide for methods and tools to quickly estimate the power consumption at the first steps of a system design. We introduce multi-level power models and show how to use them at differen...
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Article
Open AccessA Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis
This paper presents a metric-based approach for estimating the hardware implementation effort (in terms of time) for an application in relation to the number of linear-independent paths of its algorithms. We e...
