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  1. No Access

    Chapter and Conference Paper

    A HIPERLAN/2 — IEEE 802.11a Reconfigurable System-on-Chip

    In this paper the design of a partly reconfigurable System-on-Chip (SoC) for wireless LANs is described. The reconfigurable System-on-Chip will realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. Th...

    S. Blionas, K. Masselos, C. Dre, C. Drosos… in Field-Programmable Logic and Applications:… (2002)

  2. No Access

    Chapter and Conference Paper

    Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations

    A run-time reconfiguable array of multipliers architecture is introduced. The novel multiplier can be easily reconfigured to trade bitwidth for array size, thus maximizing the utilization of available hardware...

    G. Koutroumpezis, K. Tatas, D. Soudris… in Field-Programmable Logic and Applications:… (2002)

  3. No Access

    Chapter and Conference Paper

    Instruction Level Energy Modeling for Pipelined Processors

    A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the ...

    S. Nikolaidis, N. Kavvadias, T. Laopoulos… in Integrated Circuit and System Design. Powe… (2003)

  4. No Access

    Chapter and Conference Paper

    Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms

    A methodology for the power-efficient implementation of multimedia kernels based on reconfigurable hardware (FPGA) is introduced. The methodology combines various types of algorithmic transformations and high-...

    K. Tatas, K. Siozios, D. Soudris… in Integrated Circuit and System Design. Powe… (2003)

  5. No Access

    Chapter and Conference Paper

    Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform

    Due to the combination of flexibility and realization efficiency, reconfigurable hardware has become a promising implementation alternative. In the context of the IST-AMDREL project, a mixed granularity reconf...

    K. Masselos, S. Blionas, J-Y. Mignolet… in Integrated Circuit and System Design. Powe… (2004)

  6. No Access

    Chapter and Conference Paper

    A Multi-level Validation Methodology for Wireless Network Applications

    This paper presents the validation methodology established and ap-plied during the development of a wireless LAN application. The target of the development is the implementation of the hardware physical layer ...

    C. Drosos, L. Bisdounis, D. Metafas… in Integrated Circuit and System Design. Powe… (2004)

  7. Article

    Open Access

    Microarchitecture of a MultiCore SoC for Data Analysis of a Lab-on-Chip Microarray

    This paper presents a reconfigurable architecture of a lab-on-chip (LoC) microarray device capable to process data either in genoty** or in gene expression applications in a fraction of the time that is requ...

    G. Kornaros, S. Blionas in EURASIP Journal on Advances in Signal Processing (2008)

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