Abstract
A run-time reconfiguable array of multipliers architecture is introduced. The novel multiplier can be easily reconfigured to trade bitwidth for array size, thus maximizing the utilization of available hardware, multiply signed or unsigned data, and uses part of its structure when needed. The proposed reconfigurable circuit consists of an array of m×m multipliers, a few arrays of adders each adding three numbers, and switches. Also small blocks for the implementation of the reconfiguration capabilities, mentioned above, consist of adders, multiplexers, inverters, coders and registers. The circuit reconfiguration can be done dynamically through using only a few control bits. The architecture design of the reconfigurable multiplier, with hardware equivalent to one 64×64 bit high precision multiplier, which can be dynamically reconfigured to produce an array of the products in different forms is described in detailed manner.
This work was partially supported by the project AMDREL IST-2001-34379 funded by EC.
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References
J. Hauser and J. Wawrzynek: Garp: A MIPS Processor with a Reconfigurable Coprocessor;Proc. IEEE FCCM’ 97, Napa, CA, USA, April 16–18, 1997.
E. Mirsky, A. De Hon: MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources; Proc. IEEE FCCM’ 96, NAPA, CA, USA, April 17–19, 1996.
T. Miyamori and K. Olokotun: REMARC: Reconfiguirable Multimedia Array Coprocessor; Proc. ACM/SIGDA FPGA’ 98, Monterey, Feb. 1998
H. Singh, et al.: MorphoSys: An Integrated Re-Configurable Architecture; Proceedings of the NATO RTO Symp. On System Concepts and Integration, Monterey, CA, USA, April 20-22, 1998.
J. Rabaey: Reconfigurable Computing: The Solution to Low Power Programmable DSP; Proc. ICASSP’ 97 Munich, Germany, April 1997.
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. Taylor "PipeRench: A Reconfigurable Architecture and Compiler" in IEEE Computer, Vol. 33, No. 4, April 2000.
Reiner Hartenstein, ”A Decade of Reconfigurable Computing: a Visionary Retrospective”, Embedded Turorial, Asia-Pacific DAC, 2001.
Rong Lin, A Run-Time Reconfigurable Array of Multipliers Architecture, in Proc. of 8th Reconfigurable Architectures Workshop (RAW 2001, in conjuction with International Parallel & Distributed Processing Symposium 2001, San Fransisco, April 2001.
Behrooz Parhami, “Computer Arithmetic: Algorithms and Hardware Designs,” Oxford University Press, 2000.
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Koutroumpezis, G., Tatas, K., Soudris, D., Blionas, S., Masselos, K., Thanailakis, A. (2002). Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_105
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DOI: https://doi.org/10.1007/3-540-46117-5_105
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