Skip to main content

1 Result(s)

within Naveen Kadayinti Remove this filter

and

  1. No Access

    Article

    Effect of jitter on the settling time of mesochronous clock retiming circuits

    It is well known that timing jitter can degrade the bit error rate of receivers that recover the clock from input data. However, timing jitter can also result in an indefinite increase in the settling time of ...

    Naveen Kadayinti, Amitalok J. Budkuley… in Analog Integrated Circuits and Signal Proc… (2019)