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Chapter
Speculatively Multithreaded Architectures
Using the increasing number of transistors to build larger dynamic-issue superscalar processors for the purposes of exposing more parallelism has run into problems of diminishing returns, great design complexi...
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Chapter
Microprocessors — 10 Years Back, 10 Years Ahead
Continuing improvements in semiconductor technology — as characterized by Moore’s law — have provided computer architects with an increasing number of faster ransistors with which to build microprocessors. In ...
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Chapter and Conference Paper
Speculative Multithreaded Processors
Architects of future generation processors will have hundreds of millions of transistors with which to build computing chips. At the same time, it is becoming clear that naive scaling of conventional (supersca...
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Article
Speculative Memory Cloaking and Bypassing
We revisit memory hierarchy design viewing memory as an inter-operation communication mechanism. We show how dynamically collected information about inter-operation memory communication can be used to improve ...
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Chapter
An Architectural Characterization of Prolog Execution
We present an instruction-level profile and a higher-level operation profile obtained from simulations on a set of mid-sized Prolog programs for a load-store architecture we have developed. Our arc...
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Article
The use of intermediate memories for low-latency memory access in supercomputer scalar units
One of the prime considerations for high scalar performance in supercomputers is a low memory latency. With the increasing disparity between main memory and CPU clock speeds, the use of an intermediate memory ...
