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A Comprehensive Analysis in Recent Advances in 3D VLSI Floorplan Representations

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Advances in VLSI and Embedded Systems

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 962))

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Abstract

Floorplan is one of the most critical steps of the physical design of VLSI Design flow. Decreasing size, interconnects, power consumption, and chip leakage are always on the top priority list for consumers and researchers. This article presents the latest advancements in one of the hot research topics in VLSI Physical Design: 3D Floorplanning. A lot of research articles have been studied for this article, and only major research points from some chosen relevant to 3D architecture articles have been incorporated in this paper. The 3D VLSI floorplan field is quite vast than the 2D VLSI floorplan and is comparatively less explored. This article reviews various aspects of floorplanning that cover floorplanning based on volume, tiers, vias, TSVs, and other representations of 3D VLSI Floorplan. These techniques, when applied as algorithms, help in simplifying the problem. These algorithms help optimize results that increase the chip’s overall performance. Some of the central representations have been incorporated in Sect. 5. Conclusion with research gap and future scope is described in the end.

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Acknowledgments

This work is supported by I.K. Gujral Punjab Technical University, Kapurthala, India. The authors would like to extend their gratitude to the university for all the support.

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Authors and Affiliations

  1. Research Scholar, Department of Electronics and Communication Engineering, I.K. Gujral Punjab Technical University, Kapurthala, Punjab, 144603, India

    Rohin Gupta

  2. Department of Electronics and Communication Engineering, National Institute of Technical Teachers Training and Research, Chandigarh, 160019, India

    Sandeep Singh Gill

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  1. Rohin Gupta
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Correspondence to Rohin Gupta .

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Editors and Affiliations

  1. Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat, India

    Anand D. Darji

  2. Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat, India

    Deepak Joshi

  3. Department of Electronics and Communication Engineering, Malaviya National Institute of Technology Jaipur, Jaipur, Rajasthan, India

    Amit Joshi

  4. Department of Computer Science, Edge Hill University, Ormskirk, Lancashire, UK

    Ray Sheriff

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Gupta, R., Gill, S.S. (2023). A Comprehensive Analysis in Recent Advances in 3D VLSI Floorplan Representations. In: Darji, A.D., Joshi, D., Joshi, A., Sheriff, R. (eds) Advances in VLSI and Embedded Systems. Lecture Notes in Electrical Engineering, vol 962. Springer, Singapore. https://doi.org/10.1007/978-981-19-6780-1_20

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  • DOI: https://doi.org/10.1007/978-981-19-6780-1_20

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  • Online ISBN: 978-981-19-6780-1

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