Abstract
Floorplanning is a crucial phase in the physical design. It estimates the overall chip area, the interconnects, and the latency by determining the shape, size, and placements of the modules in a chip. The VLSI floorplan problem has been addressed by several researchers using a variety of heuristics and metaheuristic techniques. An essential component of the floorplan stage is the floorplan representation. The VLSI floorplanning problem is surveyed in this paper, along with a comparison of the various optimisation algorithms (like Simulated Annealing, Particle Swarm Optimisation, Differential Evolution, Ant Colony Optimisation as optimisation algorithms) and the representations involved in the VLSI floorplanning problem.
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Lobiyal, M.K., Singh, S. (2024). VLSI Floorplan Area Optimisation Technique. In: Mehta, G., Wickramasinghe, N., Kakkar, D. (eds) Innovations in VLSI, Signal Processing and Computational Technologies. WREC 2023. Lecture Notes in Electrical Engineering, vol 1095. Springer, Singapore. https://doi.org/10.1007/978-981-99-7077-3_5
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DOI: https://doi.org/10.1007/978-981-99-7077-3_5
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