Abstract
In this work, a vertical gallium nitride (GaN)-based trench MOSFET on 4-inch free-standing GaN substrate is presented with threshold voltage of 3.15 V, specific on-resistance of 1.93 mΩ·cm2, breakdown voltage of 1306 V, and figure of merit of 0.88 GW/cm2. High-quality and stable MOS interface is obtained through two-step process, including simple acid cleaning and a following (NH4)2S passivation. Based on the calibration with experiment, the simulation results of physical model are consistent well with the experiment data in transfer, output, and breakdown characteristic curves, which demonstrate the validity of the simulation data obtained by Silvaco technology computer aided design (Silvaco TCAD). The mechanisms of on-state and breakdown are thoroughly studied using Silvaco TCAD physical model. The device parameters, including n−-GaN drift layer, p-GaN channel layer and gate dielectric layer, are systematically designed for optimization. This comprehensive analysis and optimization on the vertical GaN-based trench MOSFETs provide significant guide for vertical GaN-based high power applications.
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Introduction
Wide-bandgap GaN-based power devices have been regarded as the great potential candidates for the next generation efficient power electronics and compact power systems, owing to the superior material properties such as high electron mobility, large breakdown field strength and high thermal stability [1,2,3,4,5]. Compared with high electron mobility transistors (HEMTs) [6,7,8,9,10,11] and current aperture vertical electron transistors (CAVETs) [12,13,14,15], GaN-based trench metal oxide semiconductor field effect transistors (MOSFETs) [16,17,18] are more competitive to realize intrinsically normally-off operation with higher current density, lower specific on-resistance (Ron,sp) and lower current collapse. Moreover, GaN-based trench MOSFETs possess relatively simple manufacturing process and do not need the regrowth of AlGaN/GaN layers [19, 20].
The development of lateral GaN-based MOSFETs has approximately come to saturation, due to the breakdown voltage (VBR) limited by the length of lateral drift region. Although the growth of length can increase VBR, the size of device enlarges, leading to reduction of the effective current density per unit chip area. In contrast, vertical GaN-based devices have been fully advanced. Under the same required VBR and amperage rating, smaller size and less cost can be realized on vertical GaN-based MOSFETs when make a contrast with lateral GaN MOSFETs [21]. In comparison with Si, Sapphire, SiC and Diamond substrate, the MOSFETs on free-standing GaN substrate can greatly reduce the probability of the high-density trap states and non-linearity contributed by lattice mismatch while operating at high power [22].
More studies have made great progress in VBR, Ron,sp and device reliability for GaN vertical MOSFETs in recent years. Floating P-body had been introduced in the N−-GaN drift region to form “P-body/N-drift” junction via TCAD simulation for the improvement of VBR of the enhancement-mode vertical GaN MOSFET [ High-quality, large-size and less-expensive GaN substrates are crucial for the progress of vertical GaN power devices. More techniques were proposed to optimize the growth of bulk GaN crystals, such as halide vapor phase epitaxy (HVPE), high nitrogen pressure solution (HNPS), basic and acidic ammonothermal, Na-flux method and near atmospheric pressure solution growth [27, 28]. HVPE is the main method for mass fabrication of GaN crystals, due to its high grow rate, high purity, high process repeatability and easy do**. The transparent 4-inch freestanding GaN wafer grown by HVPE with 13 points position for test is shown in Fig. 1a. We utilized a 420-μm-thick free-standing n+-GaN substrate in the device fabrication with the average mobility of 614 cm2·V−1·s−1 and the average dislocation density of 1.94 × 106 cm−2 at the top surface, as determined by contactless Hall measurement and cathodoluminescence (CL). The test result and CL image of the epitaxial layer are presented in Fig. 1b, c, respectively. a Photograph of 4-inch freestanding GaN wafer, where the letters SZU can be clearly seen. b The mobility of GaN wafer. c The dislocation density and CL image of the epitaxial layer. d The fabrication process. e The schematic of energy band lined-up at the Al2O3/GaN heterointerface. f 3D drawing structure and g micrograph of the fabricated GaN TG-MOSFET The fabrication process of the GaN TG-MOSFETs discussed in this work is shown in Fig. 1d. The epitaxial growth began with 12-µm lightly doped 8.0 × 1015 cm−3 n−-GaN as the drift region. A 1.0-µm heavily doped p-GaN with a do** density of 1.0 × 1018 cm−3 was deposited as the channel region. Thereafter, a 0.2-µm-thick heavily doped n+-GaN with a do** density of 3 × 1018 cm−3 was grown as the source contact layer. The device fabrication process started with the formation of 0.2-μm-deep vertical trench and 1.7-μm-deep vertical mesa for p-body and gate contacts by using Cl2-based gases in reactive ion etching (RIE) at 15 W power, respectively. A 16-nm-thick Al2O3 film was deposited by atomic layer deposition (ALD) as gate dielectric. High-quality and stable MOS interface with low-density trap states is essential for GaN TG-MOSFETs. A two-step process, including simple acid cleaning and a following (NH4)2S passivation, was required to drastically reduce the interface states and border traps [29]. The source and drain electrodes with Ti/Al were annealed at 550 °C for 5 min in N2 ambient for ohmic contacts. The gate and p-body electrodes were composed of Ti/Au and Palladium, respectively. A 400-nm-thick SiO2 film was deposited by plasma enhanced chemical vapor deposition (PECVD) as the passivated isolation mesa. Finally, field plate termination was employed to impair the peak electric field crowded at the edge of PN junction around the isolation mesa. The Al-based field plate was connected to the source electrode. The schematic of energy band lined-up at the Al2O3/GaN heterointerface in Fig. 1e. The forbidden band of GaN was exactly contained in that of Al2O3, where the deviations of the conduction band and valence band were 3.38 eV and 0.22 eV, respectively. It revealed that Al2O3 could maintain excellent insulation with GaN for electrons, which greatly reduced gate leakage current and improved device performance. The 3D drawing structure and parameters needed for optimization are shown in Fig. 1f. Figure 1g shows the micrograph of the device. The hexagonal crystal structure contained the outward vertical C axis, three horizontal axes a1, a2 and a3, and crystal planes in various directions. The physical simulation models concerned for simulation were the parallel electric field-dependent mobility model, concentration-dependent mobility model, low field mobility model, Shockley–Read–Hall recombination model, Auger recombination model, impact ionization model, energy bandgap narrowing model and trap model [26, 29,30,31]. The main physical models and parameter values for simulation are shown in Table 1. For GaN simulation, Si donors and Mg acceptors were not completely ionized at room temperature since their high activation energies, especially for Mg-doped p-type GaN [32,33,34]. Thus, according to Fermi–Dirac distribution, the incomplete ionization model was incorporated in the simulation for accurately reproducing the breakdown voltage. The ionized donors and acceptors impurity concentrations were given as follows Here, gD and gA are the appropriate degeneracy factors for conduction and valence bands. ED,0 and EA,0 are the donor and acceptor ionization energy at very low do** levels. θn and θp are constants accounting for geometrical factors as well as for the properties of the material. Low field mobility model is the result of fitting Caughey Thomas like model to Monte Carlo data [26, 32]. It can be defined as where µ1, µ2 are the minimum and maximum mobility, ρ, β1, β2, β3, β4, are all temperature dependent fitting parameters, Nref is the reference do** level and N is the donor concentration. The Poisson’s equations and Current continuity equation were essential for the analysis of simulation [35]. As in semiconductor PN junction, avalanche breakdown occurred when the impact ionization integral reached unity where In is the impact ionization integral of electrons. The utilized ionization rate model of electrons and holes are variation of the classical Chynoweth model [36], which based upon the following expressions, Here, E is the electric field in the direction of current flow at the p-GaN channel layer in the structure. Various group has reported impact ionization coefficients to accurately predict the breakdown of GaN power devices in recent years [37,38,39,40,41]. The coefficients AN, AP, BN, BP, BETAN and BETAP of the impact ionization model in this work were determined by referring to the experiments above. In this study, the work was mainly carried out by TCAD. The data obtained by simulation had been calibrated with the result of experiment on GaN TG-MOSFET shown in the third part. The comprehensive analysis and optimization design on Ldrift, Ltrench, Ldielectric, Lchannel, Na and Nd of devices were demonstrated in the fourth part, respectively. The initial device parameters of simulation model were set as follows: Nd = 8.0 × 1015 cm−3, Na = 1.0 × 1018 cm−3, Ldrift = 12 μm, Ltrench = 0.5 μm, Lchannel = 1.0 μm, and Ldielectric = 16 nm. The interface state could capture the free electrons in the channel and formed the negative interface charge, leading to the decrease of the number of free electrons and the increase of Ron,sp. A low density of interface state was beneficial to reduce Ron,sp and switch loss. The interface state in the simulation was defined as 1011 cm−2·eV−1 by referring to the previous work [Analysis the Influence of n−-GaN Drift Layer As shown in Fig. 7a, VBR increased and saturated at a certain value as Ldrift increased with different initial conditions. The phenomenon that DR extended and saturated with the growth of Ldrift caused the VBR increased and saturated. Conversely, VBR decreased with the growth of Nd. The situation was equivalent to the effect of the do** concentration in the low-doped side of the PN single junction diode on the VBR, which demonstrated that the value of Nd was inversely proportional to VBR. It implied that VBR prematurely saturated at thin Ldrift with high Nd. Low Nd had larger DR than high Nd due to the IGR of electron was low. Large DR could withstand high voltage and prevent electron absorbing electric field energy to reach breakdown. The change of Ron,sp was mainly caused by the variation of Rdrift (Ron,sp of n−-GaN drift layer). The Ron,sp decreased with the increase of Nd and decrease of Ldrift, respectively. Ron,sp decreased from 2.55 mΩ·cm2 to 1.56 mΩ·cm2 and VBR reduced from 2558 to 1997 V as Nd increased from 8.0 × 1015 cm−3 to 1.0 × 1016 cm−3 under Ldrift = 12 μm. In Fig. 7b, the obtained peak FOM were 2.76 GW/cm2, 2.69 GW/cm2 and 2.62 GW/cm2 under Ldrift = 16 μm, Ldrift = 12 μm, and Ldrift = 10 μm with the growth of Nd, respectively. It demonstrated that the optimal FOM could be obtained under the low Nd and thick Ldrift. In contrast, the change of Nd and Ldrift had no effect on Vth, and it remained at 3.15 V. The impact on Ron,sp and VBR were obvious by the change of Nd and Ldrift, while hardly influenced Vth. a Simulated Ron,sp and VBR of the device versus Ldrift and Nd. b Vth and FOM as a function of Ldrift and Nd. c Simulated Ron,sp and VBR of the device versus Ltrench and Nd. d Vth and FOM as a function of Ltrench and Nd. In (a)–(d), the square, circle and triangle curves were simulated under Nd = 6.0 × 1015 cm−3, Nd = 8.0 × 1015 cm−3 and Nd = 1.0 × 1016 cm−3, respectively With the increase of Ltrench from 0.1 to 1.0 µm in Fig. 7c, d, Ron,sp continuously decreased. In contrast, VBR and FOM first increased and then decreased as the advance of Ltrench, finally reaching peak value at Ltrench = 0.2 µm. The obtained peak FOM were 3.15 GW/cm2, 3.45 GW/cm2 and 3.64 GW/cm2 under Nd = 6.0 × 1015 cm−3, Nd = 8.0 × 1015 cm−3, and Nd = 1.0 × 1016 cm−3, respectively. The impact of Ltrench on FOM was apparent when it was thin. The variety of Nd and Ltrench also made little difference on Vth. Vth showed independence for the change of Nd, Ldrift and Ltrench, due to the p-type channel region. The effects of the Lchannel and Na of p-GaN channel layer were investigated based on Ldrift = 12 μm and Ltrench = 0.2 μm of n−-GaN drift layer. The change of Ron,sp was mainly caused by the variation of Rchannel (Ron,sp of p-GaN channel layer). The curves of Ron,sp showed continuous rising trend with the enhancement of Lchannel as shown in Fig. 8a. As Na increased from 2.0 × 1017 cm−3 to 3.0 × 1018 cm−3 under Lchannel = 1.0 μm, Ron,sp showed increasing trends from 1.94 mΩ·cm2 to 1.96 mΩ·cm2. The effect on the Ron,sp brought by the variety of Lchannel was little. The growth of Na could enlarge the VBR from 65 to 2632 V under 0.1 um. VBR increased and saturated at Lchannel = 0.8 μm under Na = 2.0 × 1017 cm−3. In contrast, VBR increased and saturated at Lchannel = 0.2 μm under Na = 8.0 × 1017 cm−3 and Na = 1.0 × 1018 cm−3, respectively. Moreover, VBR kept saturated from 0.1 μm to 1.0 μm of Lchannel under Na = 3.0 × 1018 cm−3. The high enough value of Lchannel · Na could achieve avalanche breakdown, which could be seen from the saturated VBR. On the contrary, the unsaturated VBR was known as punch-through breakdown. Similarly, the variation trend of FOM was the same as VBR. The peak FOM obtained was 3.59 GW/cm2. Vth grew from 1.19 V to 7.93 V under Lchannel = 1.0 μm with the increase of Na as shown in Fig. 8b. The change of Na had a marked effect on Vth, whereas the impact brought by the variety of Lchannel on Vth was negligible. a Simulated Ron,sp and VBR of the device versus Lchannel and Na. b Vth and FOM as a function of Lchannel and Na. In (a) and (b), the square, rhombus, circle and triangle curves were simulated under Na = 2.0 × 1017 cm−3, Na = 8.0 × 1017 cm−3, Na = 1.0 × 1018 cm−3 and Na = 3.0 × 1018 cm−3, respectively. c Simulated Ron,sp and VBR of the device versus Ldielectric. d Vth and FOM as a function of Ldielectric The impact of the Ldielectric was researched based on Lchannel = 1.0 μm. The growth of Ldielectric would reduce Cox and electron concentration of channel layer under on-state condition, resulting in larger Ron,sp and Vth. Ron,sp increased from 1.92 mΩ·cm2 to 2.24 mΩ·cm2 and Vth enhanced from 1.87 V to 8.97 V for Ldielectric increasing from 8 to 50 nm as shown in Fig. 8c, d. Ldielectric had no effect on VBR, leading to the reduction of FOM from 3.63 GW/cm2 to 3.10 GW/cm2. In this work, we analysed the performance of the fabricated GaN TG-MOSFET on 4-inch free-standing GaN substrate by Silvaco TCAD. The mechanisms of on-state and breakdown have been well studied. The key device parameters have been thoroughly researched considering the trade-off between Ron,sp and VBR. The normally off operation and high breakdown voltage show enormous potential to provide a bright future application for vertical GaN-based high power electronics.Experiment and Simulation Approach
Results and Discussion
Analysis the Impact of p-GaN Channal and Dielectric
Conclusion
Availability of data and materials
All data generated or analyzed during this study are included within the article.
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We thank the reviewers for their valuable comments.
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This work was supported by National Natural Science Foundation of China (61974144, 62004127), Key-Area Research and Development Program of Guangdong Province 2020B010169001, Guangdong Science Foundation for Distinguished Young Scholars, and Science and Technology Foundation of Shenzhen JSGG20191129114216474.
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XL and WH conceived the idea. ZL and JL did the experiment part of this work. JL and FL did the simulation part of this work. JW collected and sorted out the literatures. BW, MW, NL, H-CC, and H-CK took place in analysis and discussion. Jian Li drafted the manuscript. **nnan Lin and **gbo Li provided professional assistance in the revised manuscript. All authors read and approved the final manuscript.
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He, W., Li, J., Liao, Z. et al. 1.3 kV Vertical GaN-Based Trench MOSFETs on 4-Inch Free Standing GaN Wafer. Nanoscale Res Lett 17, 14 (2022). https://doi.org/10.1186/s11671-022-03653-z
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DOI: https://doi.org/10.1186/s11671-022-03653-z