A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

Abstract

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

Introduction

Resistance switching or memristive devices are metal-insulator-metal structures that can switch between at least two different resistance states upon application of an electrical impulse (voltage or current). Although the phenomenon of resistance switching has been known since the 1960 s, research interest has significantly grown in the last decade after resistance switching devices were identified not only as one of the leading candidates for next generation memory^{1,2,3,4,5,6,7} but also for analog computation^8,9,10, neuromorphic circuits^{11,12,13,14,15}, reconfigurable logic^{Figure 5c(ii) shows a gradual increase of channel 1 (layer 1) weight from 0.39 mS to 0.48 mS in 5 steps, using the tuning algorithm. The evolution of the output waveform is shown in Fig. 5c(i), which confirms the correct operation. The amplitude (peak-peak) of the output current for the layer 1 component changes from 72 μA to 95 μA as a result (see Supplementary Figure 14b). In the next step, the state of the device in layer 1 is kept unchanged while the device in layer 2 is gradually turned on (Fig. 5c(v)). The corresponding output waveforms are displayed in Fig. 5c(iv). As expected, as the weight for channel 2 increases the amplitude of the high-frequency component in the output waveform increases. As shown in Supplementary Figure 14f, the layer 2 component (peak-peak) changes from 10–50 μA. The margins for the change in output current components for both the layer 1 and layer 2 devices are ~5 μA or more (Supplementary Figure 14) and it is to be noted that this margin can be easily adjusted by the tuning procedure. These results indicate that the devices in each layer in the 3D CMOL crossbars can be controlled independently and used for matrix multiplication operation. However, practical implementation of high bandwidth multiply-add operation using 3D CMOS/memristor crossbars will also require overcoming the challenges due to finite line resistance, sneak-path and other sources of noise. Increase in the number of layers in a 3D crossbar is equivalent to increasing the size of a 2D crossbar array, thereby also increasing the sneak-currents33 or train the hardware through supervised or unsupervised learning schemes14,34. A detailed analysis of the effect of sneak-paths in 3D hybrid memristor/CMOS and accurate benchmarking is beyond the scope of this work. Development of a selector technology can also be a possible solution. We will investigate these avenues in our future work.}

Figure 5: Dot-product operation in the integrated 3D memristive crossbars.

(a) Schematic of the set-up for the dot-product operation utilizing two devices in two different layers of the 3D crossbar, (b) An example of the dot product operation with two sinusoidal inputs applied to two devices in a 3D crossbar and the device in layer 1 being programmed to decreasing conductance values, (c) (i) evolution of the output waveform with the weight of the device in layer 1 changing (ii) and the weight for the device on the 2nd layer being kept constant (iii); (iv) evolution of the output waveform when weight of the device in layer 1 is kept constant (v) while layer 2 device changes it’s state (weight) (vi).

In summary, we demonstrate the first 3D CMOL hybrid circuit with 3D memristive crossbars monolithically integrated on a CMOS substrate. High integration yield in terms of good electrical contact between the memristive components and the CMOS substrate was achieved by planarization of the CMOS chips. The integrated 3D crossbars can be fully controlled by the underlying CMOS circuitry. The memristive devices display forming-free switching with low voltage operation. They are analog tunable using a write-and-verify algorithm. The multi-level control of the states for the memristive devices allows them to be used in multiply-add operations where their conductance values can be used as controllable weights. Demonstration of multiply-add operation utilizing memristive devices both in the 1^st and 2^nd layer of the 3D crossbars opens up promise for ultra-high bandwidth multiply-add engines with high density memristor/CMOS 3D hybrid circuits.

Methods

Preparation of planarization holder

The CMOS chips used in this experiment have a dimension of 5 mm × 5 mm and a thickness of 256 μm. Thickness of a 4 inch Si wafer with initial thickness of ~260 μm (+0−4 μm) is reduced by 6–10 μm (depending on the initial thickness) using deep-Si Reactive Ion Etching (DRIE) to have a final thickness of ~254 μm. The wafer is then polished by CMP in SF1 slurry (alkaline colloidal silica) for 4 mins to remove the roughness generated by the DRIE process. A 3 μm SiO₂ film is then deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) on the wafer. A 5.5 mm window is patterned on the oxide by photolithography with negative resist (AZnLOF2020) and using a 5.5 mm Si piece as the mask. The oxide in the window region is etched back with CHF3 plasma. The wafer is then subjected to DRIE to completely etch Si within the window to make a 5.5 mm × 5.5 mm hole in the Si wafer.

Chemical mechanical planarization of the chip

The as-received chip has a 1.3 μm scratch-protect oxynitride layer with unknown composition (undisclosed from the Foundry). Due to the unknown composition/quality of the oxynitride it is difficult to precisely control processing of this layer. Therefore we completely remove this layer and use a planarization dielectric of known quality/composition. After completing removing the oxynitride layer by dry etching in CHF₃ plasma, the organic residues were removed by cleaning in AZ300T for 15 minutes. Next the CMOS pads in the active region are covered with Ti/Au (10/100 nm) to prevent oxidation of Al. A 2.5 μm SiO₂ layer is then deposited by Inductively Coupled Plasma based PECVD (ICP-PECVD) at low temperature (50 °C). The planarization holder is then crystal bonded on a second Si substrate and the CMOS chip is placed in the middle of the holder. The entire ensemble was then polished in CMP with SF1 slurry for 4 mins. After CMP the final topography of the chip is verified by atomic force microscopy (AFM). The oxide thickness on top of the CMOS pads post-CMP is measured by a reflectance measurement unit. The post-CMP oxide thickness is ~1.5 μm across the chip. Next the planarization oxide (SiO₂) is etched back to the desired thickness (180 nm).

3D memristive crossbar fabrication

4 × 4 μm² via holes for contact between the BEs of the crossbars and the CMOS pads are first created by photolithography and CHF₃ plasma etching through the 180 nm planarization oxide. Next, Ta/Pt (5/60 nm) BEs for layer 1 devices (width 2 μm) were patterned by photolithography and E-beam evaporation. The Al₂O₃/TiO_x (3/30 nm) switching stack is deposited by reactive sputtering in Ar/O₂ plasma. Stoichiometry of the TiO_x layer was controlled by controlling the O₂ flow. Next, via holes (4 × 4 μm²) for contact between the TEs and CMOS pads are created by photolithography and dry etching in CHF₃ plasma. TEs of Ti/Pt (15/60 nm) are defined by optical lithography and E-beam evaporation. After fabrication of the first crossbar layer an isolation oxide of 200 nm is deposited by ICP- PECVD. The 2^nd layer of crossbars is fabricated by performing the same fabrication steps used for layer 1, namely patterning of BE via holes, deposition of Ta/Pt BEs, deposition of the switching oxide stack, patterning of TE via holes and defining the Ti/Pt TEs. In a final lithography step, via holes are opened on the wire-bonding pads by photolithography and CHF₃ plasma etching. The chip is then annealed at 300 °C for 15 mins in forming gas (N₂ + H₂). The processed chip was wire bonded and packaged in a commercial facility before electrical measurements were performed.