Abstract
As the technology advances in the field of VLSI physical design at rapid pace, there is a demand to incorporate the maximum number of transistors and modules within the relatively minimum area. Generally reduction of silicon chip area is the goal and objective of the Placement in Physical Design. Before the placement is done, there is a procedure to plan the physical and technical location of the modules which is nothing but Floorplanning. To minimize the Placement area in Physical Design one has to do the Floorplanning effectively as a ground work for the VLSI Placement. This minimization can be done using Optimization algorithms which are the tools in various areas of research and technology. In this paper, Harmony Search (HS) Algorithm which is inspired by the music playing phenomenon of the musicians is implemented to achieve the goal of this work. The objective here is to minimize the floorplan area which will be the fruitful ground work for the VLSI placement in Physical Design automation. The MATLAB code for the Harmony Search Algorithm is simulated and the results are validated through the standard MCNC (Microelectronics Centre of North Carolina) benchmark circuits for better analysis.
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Karimullah, S., Vishnu Vardhan, D., Basha, S.J. (2020). Floorplanning for Placement of Modules in VLSI Physical Design Using Harmony Search Technique. In: Kumar, A., Paprzycki, M., Gunjan, V. (eds) ICDSMLA 2019. Lecture Notes in Electrical Engineering, vol 601. Springer, Singapore. https://doi.org/10.1007/978-981-15-1420-3_197
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DOI: https://doi.org/10.1007/978-981-15-1420-3_197
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