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  1. No Access

    Article

    Accelerating temporal verification of Simulink diagrams using satisfiability modulo theories

    Automatic verification of programs and computer systems with input variables represents a significant and well-motivated challenge. The case of Simulink diagrams is especially difficult, because there the inpu...

    Petr Bauch, Vojtěch Havel, Jiří Barnat in Software Quality Journal (2016)

  2. No Access

    Chapter and Conference Paper

    On Clock-Aware LTL Properties of Timed Automata

    We introduce the Clock-Aware Linear Temporal Logic (CA-LTL) for expressing linear time properties of timed automata, and show how to apply the standard automata-based approach of Vardi and Wolper to check for the...

    Peter Bezděk, Nikola Beneš, Vojtěch Havel… in Theoretical Aspects of Computing – ICTAC 2… (2014)

  3. No Access

    Chapter and Conference Paper

    LTL Model Checking of LLVM Bitcode with Symbolic Data

    The correctness of parallel and reactive programs is often easier specified using formulae of temporal logics. Yet verifying that a system satisfies such specifications is more difficult than verifying safety ...

    Petr Bauch, Vojtěch Havel, Jiří Barnat in Mathematical and Engineering Methods in Co… (2014)

  4. Chapter and Conference Paper

    DiVinE 3.0 – An Explicit-State Model Checker for Multithreaded C & C++ Programs

    We present a new release of the parallel and distributed LTL model checker DiVinE. The major improvement in this new release is an extension of the class of systems that may be verified with the model checker, wh...

    Jiří Barnat, Luboš Brim, Vojtěch Havel, Jan Havlíček… in Computer Aided Verification (2013)

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