Reliable Software for Unreliable Hardware
A Cross Layer Perspective
Chapter
For generating and executing dependable software, the effects of hardware layer faults at the software layer have to be accurately analyzed and modeled. This requires relevant information from the hardware and...
Chapter
The drive for automation and constant monitoring has led to rapid development in the field of Machine Learning (ML). The high accuracy offered by the state-of-the-art ML algorithms like Deep Neural Networks (D...
Chapter
Power-constrained fault-tolerance has emerged as a key challenge in the deep sub-micron technology. Multi-/many-core chips can support different hardening modes considering variants of redundant multithreading (R...
Chapter
The Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technolog...
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Fault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead. On the other ha...
Chapter
The tremendous growth of interconnectivity and dependencies of physical and cyber domains in cyber-physical systems (CPS) makes them vulnerable to several security threats like remote cyber-attacks, hardware, ...
Chapter
Video processing applications are inherently error resilient. This resilience comes from the fact that: (1) inputs obtained are noisy and highly correlated in the spatial and temporal domains, (2) probabilisti...
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Neural networks (NNs) are the state of the art for many artificial intelligence (AI) applications. However, in order to facilitate the training process, most of the neural networks are over-parameterized and r...
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The exponentially growing rates of data production in the current era of internet of things (IoT), cyber-physical systems (CPS), and big data pose ever-increasing demands for massive data processing, storage, ...
Chapter
Multipliers are an integral block of a wide range of error-resilient applications like audio, image, and video processing, and machine learning. However, these multiplier architectures are computationally comp...
Book
Chapter
Scaling down the transistor dimensions has led modern systems to become more and more susceptible towards various types of reliability threats such as soft errors, design-time process variation, and run-time a...
Chapter
This chapter presents the background knowledge regarding different sources of the emerging reliability threats (i.e., soft errors, process variation, and aging-induced effects), the related work on soft error ...
Chapter
In order to estimate the reliability at the software program- level while accounting for the knowledge from the underlying hardware layers, this chapter presents different reliability estimation models that ar...
Chapter
The multiple compiled function versions generated in Chap. 5 are leveraged by the reliability-driven system software to exploit the vulnerability vs. performance tradeof...
Chapter
Embedded computing systems are ubiquitous and have been widely deployed in many application domains like security, consumer, internet-of-things, mission-critical, and airborne applications. The current and eme...
Chapter
The main problem targeted in this manuscript is to reduce the software programs’ susceptibility to soft errors on unreliable or partially reliable hardware, and to improve the reliability of the overall system...
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State-of-the-art has primarily exploited the compiler-level techniques for improving the performance and energy. This chapter aims at enabling reliability-driven compilation enabled by the instruction-level re...
Chapter
This chapter presents reliability improvement results of the proposed cross-layer reliability optimization flow (integrating all the novel contributions of this manuscript) compared to state-of-the-art single-...