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Article
Design optimization of the quantization and a pipelined 2D-DCT for real-time applications
The Discrete Cosine Transform (DCT) is one of the most widely used techniques for image compression. Several algorithms are proposed to implement the DCT-2D. The scaled SDCT algorithm is an optimization of the...
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Article
FPGA realization of high performance large size computational functions: multipliers and applications
In this paper, efficient design methodologies and systematic approaches for realizing large size signed multipliers based on the use of small-size embedded blocks in FPGAs are presented. Two algorithms, delay ...
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Article
FPGA-Based Efficient Design Approaches for Large Size Two’s Complement Squarers
This paper presents two optimized design approaches of two’s complement large size squarers using embedded multipliers in FPGAs. The realization of one of the approaches is based on Baugh–Wooley’s algorithm an...
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Article
Efficient Realization of Large Size Two’s Complement Multipliers Using Embedded Blocks in FPGAs
This paper presents an optimized design approach for two’s complement large size multipliers using smaller size embedded multiplier blocks available as resources in field programmable gate arrays (FPGAs). The ...
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Chapter and Conference Paper
Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints
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Chapter and Conference Paper
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs
Assigning computational elements to low supply voltages can reduce dynamic power dissipation, but increase execution delays. The problem of reducing dynamic power consumption by assigning low supply voltages t...
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Chapter and Conference Paper
Minimizing Variables’ Lifetime in Loop-Intensive Applications
In this paper, we address a set of research problems regarding loopintensive applications. The first problem consists of minimizing variables’ lifetime under timing constraints. Any variable that is alive for ...
