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Book
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Chapter
Introduction
Smart Systems represent a broad class of systems defined as intelligent, miniaturized devices incorporating functionality like sensing, actuation, and control. In order to support these functions, they must in...
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Article
Reusing RTL Assertion Checkers for Verification of SystemC TLM Models
The recent trend towards system-level design gives rise to new challenges for reusing existing (RTL) intellectual properties (IPs) and their verification environment in (TLM). While techniques and tools to abs...
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Article
On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation
The paper proposes an integrated methodology to abstract already existing heterogeneous IPs into SysML behavioral equivalent models. This approach aims at integrating the abstracted components with partially s...
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Article
On the Reuse of TLM Mutation Analysis at RTL
Mutation analysis has gained consensus during the last decades as being an efficient technique for measuring the quality of SW testbench. More recently, it has been efficiently applied for validating testbench...
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Article
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Functional verification techniques based on fault injection and simulation at register-transfer level (RTL) have been largely investigated in the past years. Although they have various advantages such as scala...
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Article
HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels
SystemC is the de-facto standard language for system-level modeling, architectural exploration, performance analysis, software development, and functional verification of embedded systems. Nevertheless, it has...
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Article
Open AccessHIFSuite: Tools for HDL Code Conversion and Manipulation
HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language ...