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Chapter
Automatic Tuning of CUDA Execution Parameters for Stencil Processing
Recently, Compute Unified Device Architecture (CUDA) has enabled Graphics Processing Units (GPUs) to accelerate various applications. However, to exploit the GPU’s computing power fully, a programmer has to ca...
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Chapter and Conference Paper
Analysing the Performance Improvements of Optimizations on Modern HPC Systems
Recently, there are many types of supercomputing systems being equipped with vector processors, scalar processors, and accelerators as processing elements of the systems. Although all kinds of calculations can...
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Chapter and Conference Paper
Performance Evaluation of a Next-Generation CFD on Various Supercomputing Systems
The Building-Cube Method (BCM) has been proposed as a new CFD method for an efficient three-dimensional flow simulation on large-scale supercomputing systems, and is based on equally-spaced Cartesian meshes. A...
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Chapter and Conference Paper
A Compiler-Assisted OpenMP Migration Method Based on Automatic Parallelizing Information
Performance of a serial code often relies on compilers’ capabilities for automatic parallelization. In such a case, the performance is not portable to a new system because a new compiler on the new system may ...
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Chapter and Conference Paper
Performance Evaluation of an OpenMP Parallelization by Using Automatic Parallelization Information
To exploit the potential of many core processors, a serial code is generally optimized for a particular compiler called a target compiler, so that the compiler can understand the code structure for automatic p...
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Chapter and Conference Paper
Code Optimization Activities Toward a High Sustained Simulation Performance
Rapid evolutions of HPC systems bring us a high computational capability. However, it is getting harder to exploit the potential of a HPC system due to the increases in system complexity. To create significant...
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Chapter and Conference Paper
Designing an HPC Refactoring Catalog Toward the Exa-scale Computing Era
Aiming at kee** performance portability of practical applications even in the exascale computing era, this paper presents a concept of HPC refactoring, and the design of the HPC refactoring catalog. The HPC ...
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Chapter and Conference Paper
Performance Evaluation of Compiler-Assisted OpenMP Codes on Various HPC Systems
As automatic parallelization functions are different among compilers, a serial code is often modified so that a particular target compiler can easily understand its code structure and data dependency, resultin...
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Chapter and Conference Paper
Directive Translation for Various HPC Systems Using the Xevolver Framework
This paper proposes a directive translation approach that translates a special placeholder to different directives, depending on the target HPC system. The special placeholder in an application code is used as...
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Article
Open AccessPotential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE
Achieving a high sustained simulation performance is the most important concern in the HPC community. To this end, many kinds of HPC system architectures have been proposed, and the diversity of the HPC system...
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Chapter and Conference Paper
Performance Evaluation of Tsunami Inundation Simulation on SX-Aurora TSUBASA
As tsunamis may cause damage in wide area, it is difficult to imme...
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Chapter and Conference Paper
Analysis of Relationship Between SIMD-Processing Features Used in NVIDIA GPUs and NEC SX-Aurora TSUBASA Vector Processors
This paper presents comprehensive analysis of main SIMD-processing features and computational characteristics of three high performance architectures: two NVIDIA GPU architectures (of Pascal and Volta generati...
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Article
Develo** Efficient Implementations of Shortest Paths and Page Rank Algorithms for NEC SX-Aurora TSUBASA Architecture
The main goal of this paper is to demonstrate that the newest generation of NEC SX-Aurora TSUBASA architecture can perform large-scale graph processing extremely efficiently. This paper proposes approaches, wh...
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Chapter and Conference Paper
Performance Evaluation of SX-Aurora TSUBASA by Using Benchmark Programs
This paper evaluates the basic performance of the latest vector supercomputer, SX-Aurora TSUBASA, in order to clarify its potential. First, the memory bandwidth, which is one of the features of SX-Aurora TSUBA...
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Chapter and Conference Paper
Develo** an Efficient Vector-Friendly Implementation of the Breadth-First Search Algorithm for NEC SX-Aurora TSUBASA
Breadth-First Search (BFS) is an important computational kernel used as a building-block for many other graph algorithms. Different algorithms and implementation approaches aimed to solve the BFS problem have ...
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Chapter and Conference Paper
Optimizations of DNS Codes for Turbulence on SX-Aurora TSUBASA
Direct numerical simulations (DNSs) of incompressible turbulence have been performed since the late 1960s, but simulations that reproduce strongly nonlinear turbulent flows as in the real-world have not been r...
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Chapter and Conference Paper
A Deep Reinforcement Learning Based Feature Selector
In the field of data mining and machine learning, it is a challenge for researchers and engineers to analyze and classify the high-dimensional data. In order to minimize the classification error, it is critica...
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Chapter and Conference Paper
A Dynamic Parameter Tuning Method for High Performance SpMM
Sparse matrix-matrix multiplication (SpMM) is a basic kernel that is used by many algorithms. Several researches focus on various optimizations for SpMM parallel execution. However, a division of a task for pa...
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Chapter and Conference Paper
Optimization of the Himeno Benchmark for SX-Aurora TSUBASA
This paper focuses on optimizing the Himeno benchmark for the vector computing system SX-Aurora TSUBASA and analyzes its performance in detail. The Vector Engine (VE) of SX-Aurora TSUBASA achieves a high memor...
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Chapter and Conference Paper
Performance Evaluation of SX-Aurora TSUBASA and Its QA-Assisted Application Design
In this article, we present an overview of our on-going project entitled, R&D of a Quantum-Annealing Assisted Next Generation HPC Infrastructure and its Applications. We describes our system design concept of a n...
