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Develo** an Efficient Vector-Friendly Implementation of the Breadth-First Search Algorithm for NEC SX-Aurora TSUBASA

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Parallel Computational Technologies (PCT 2020)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1263))

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Abstract

Breadth-First Search (BFS) is an important computational kernel used as a building-block for many other graph algorithms. Different algorithms and implementation approaches aimed to solve the BFS problem have been proposed so far for various computational platforms, with the direction-optimizing algorithm being the fastest and the most computationally efficient for many real-world graph types. However, straightforward implementation of direction-optimizing BFS for vector computers can be extremely challenging and inefficient due to the high irregularity of graph data structure and the algorithm itself. This paper describes the world’s first attempt aimed to create an efficient vector-friendly BFS implementation of the direction-optimizing algorithm for NEC SX-Aurora TSUBASA architecture. SX-Aurora TSUBASA vector processors provide high-performance computational power together with a world-highest bandwidth memory, making it a very interesting platform for solving various graph-processing problems. The implementation proposed in this paper significantly outperforms the existing state-of-the-art implementations both for modern CPUs (Intel Skylake) and NVIDIA V100 GPUs. In addition, the proposed implementation achieves significantly higher energy efficiency compared to other platforms and implementations both in terms of average power consumption and achieved performance per watt.

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Acknowledgement

This project was partially supported by JSPS Bilateral Joint Research Projects program, entitled “Theory and Practice of Vector Data Processing at Extreme Scale: Back to the Future” and by MEXT Next Generation High-Performance Computing Infrastructures and Applications R&D Program, entitled “R&D of A Quantum-Annealing-Assisted Next Generation HPC Infrastructure and its Applications”. The reported study was funded by RFBR, project number 19-31-27001. The reported study was supported by the Russian Foundation for Basic Research, project No. 18-29-03230. The research is carried out using the equipment of the shared research facilities of HPC computing resources at Lomonosov Moscow State University.

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Authors and Affiliations

  1. Research Computing Center of Moscow State University, Moscow, 119234, Russia

    Ilya V. Afanasyev & Vladimir V. Voevodin

  2. Tohoku University, Sendai, Miyagi, 980-8579, Japan

    Kazuhiko Komatsu & Hiroaki Kobayashi

Authors
  1. Ilya V. Afanasyev
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  2. Vladimir V. Voevodin
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  3. Kazuhiko Komatsu
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  4. Hiroaki Kobayashi
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Corresponding author

Correspondence to Ilya V. Afanasyev .

Editor information

Editors and Affiliations

  1. South Ural State University, Chelyabinsk, Russia

    Leonid Sokolinsky

  2. South Ural State University, Chelyabinsk, Russia

    Mikhail Zymbler

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Afanasyev, I.V., Voevodin, V.V., Komatsu, K., Kobayashi, H. (2020). Develo** an Efficient Vector-Friendly Implementation of the Breadth-First Search Algorithm for NEC SX-Aurora TSUBASA. In: Sokolinsky, L., Zymbler, M. (eds) Parallel Computational Technologies. PCT 2020. Communications in Computer and Information Science, vol 1263. Springer, Cham. https://doi.org/10.1007/978-3-030-55326-5_10

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  • DOI: https://doi.org/10.1007/978-3-030-55326-5_10

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  • Print ISBN: 978-3-030-55325-8

  • Online ISBN: 978-3-030-55326-5

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