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Chapter
Constructive Timing Violation for Improving Energy Efficiency
A novel technique for improving the energy efficiency of microprocessors is disclosed. This new method relies on a fault-tolerance mechanism for timing violations, based on a speculative execution technique. S...
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Chapter and Conference Paper
Reducing Energy Consumption via Low-Cost Value Prediction
Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Device engineers, circuit designers, and system architects are faced with many cha...
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Chapter and Conference Paper
Low-Cost Value Predictors Using Frequent Value Locality
The practice of speculation in resolving data dependences has been recently studied as a means of extracting more instruction level parallelism (ILP). Each instruction’s outcome is predicted by value predictor...
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Chapter and Conference Paper
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be reduced significantly, result...
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Chapter and Conference Paper
Influence of Compiler Optimizations on Value Prediction
The practice of speculation in resolving data dependences based on value prediction has been studied as a means of extracting more instruction level parallelism. There are many studies on value prediction mech...
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Chapter and Conference Paper
Intelligent console a universal user interface of a computer system
The intelligent console (INC) is a microcomputer inserted between a computer and its opetator console. Although INC is simple, it offers a very flexible user interface of a computer system. Usually, a user int...