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  1. No Access

    Article

    Dielectric Morphology and RRAM Resistive Switching Characteristics

    The connection between the bi-polar hafnia-based resistive-RAM (RRAM) operational characteristics and dielectric structural properties is considered. Specifically, the atomic-level description of RRAM, which o...

    G. Bersuker, B. Butcher, D.C. Gilmer, L. Larcher… in MRS Online Proceedings Library (2014)

  2. No Access

    Article

    Hafnia surface and high-k gate stacks

    Hafnium dioxide that belongs to a class of metal oxides with a high dielectric constant or high-k dielectrics has been recently introduced as a gate dielectric in field effect transistors. We report a theoreti...

    X. Luo, Alexander A. Demkov, O. Sharia, G. Bersuker in MRS Online Proceedings Library (2009)

  3. No Access

    Article

    Spectroscopic studies of O-vacancy defects in transition metal oxides

    Dielectrics comprised of nano-crystalline HfO2 in gate stacks with thin SiO2/SiON interfacial transition regions display significant asymmetries with respect to trap** of Si substrate injected holes and electro...

    G. Lucovsky, J. Lüning, L. B. Fleming… in Journal of Materials Science: Materials in… (2007)

  4. No Access

    Article

    On the impact of high-κ gate stacks on mobility: A Monte Carlo study including coupled SO phonon-plasmon scattering

    HfO2 based high-κ dielectrics are among the most likely candidates to replace SiO2 and the currently favoured oxinitride in the next generation of MOSFETs. High-κ materials allow the use of a thicker gate dielect...

    Giulio Ferrari, J. R. Watling, S. Roy, J. R. Barker… in Journal of Computational Electronics (2007)

  5. No Access

    Chapter and Conference Paper

    MECHANISM OF CHARGE TRAPPING REDUCTION IN SCALED HIGH-κ GATE STACKS

    Properties of the defects responsible for fast transient electron trap** phenomenon in high-k gate dielectrics were investigated. It was shown that electrons might be reversibly trapped at shallow, delocaliz...

    G. BERSUKER, B. H. LEE, H.R. HUFF, J. GAVARTIN… in Defects in High-k Gate Dielectric Stacks (2006)

  6. No Access

    Chapter and Conference Paper

    EFFECT OF CHEMICAL ENVIRONMENT AND STRAIN ON OXYGEN VACANCY FORMATION ENERGIES AT SILICONSILICON OXIDE INTERFACES

    Silicon oxide layers formed between silicon substrates and oxides with large dielectric constants (high k) play an important role in determining electrical properties for microelectronic applications such as g...

    T.M. HENDERSON, J.C. GREER, G. BERSUKER… in Defects in High-k Gate Dielectric Stacks (2006)

  7. No Access

    Chapter and Conference Paper

    Monte Carlo Study of Coupled SO Scattering in Si MOSFETs with High κ- Dielectric Gate Stacks: Hot Electron and Disorder Effects

    A Monte Carlo scheme is described for simulating electron-phonon-plasmon scattering in realistic high-κ gate stack Si MOSFETs that accounts for hot electron effects, modulation of the electron-phonon-plasmon scat...

    J. R. Barker, J. R. Watling, A. Brown… in Nonequilibrium Carrier Dynamics in Semicon… (2006)

  8. No Access

    Chapter and Conference Paper

    TOWARDS UNDERSTANDING OF PROCESSINGNANOSTRUCTURE- PROPERTY INTER-RELATIONSHIPS IN HIGHK/METAL GATE STACKS

    This paper summarizes the challenges and opportunities that lay ahead in screening candidate metal gate electrodes and their integration in a standard CMOS process in order to replace the aging poly-Si gate el...

    P. MAJHI, G. BERSUKER, B.H. LEE in Defects in High-k Gate Dielectric Stacks (2006)

  9. No Access

    Article

    Effects of Structural Properties of Hf-Based Gate Stack on Transistor Performance

    Electron traps in ALD and MOCVD HfO2 and HfSiO high-k dielectrics were investigated using both conventional DC and pulse measurements. It was found that the traps in the gate stack could be associated with defect...

    G. Bersuker, J.H. Sim, C.D. Young, R. Choi, B. H. Lee… in MRS Online Proceedings Library (2003)

  10. No Access

    Article

    Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

    We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was ...

    Joel Barnett, N. Moumen, J. Gutt, M. Gardner, C. Huffman… in MRS Online Proceedings Library (2003)

  11. No Access

    Article

    Electrical and Physical Characterization of Ultrathin Silicon Oxynitride Gate Dielectric Films Formed by the Jet Vapor Deposition Technique

    This paper describes the electrical and physical characteristics of ultrathin Jet Vapor Deposited (JVD) Silicon Oxynitride films. Capacitance-Voltage measurements indicate an equivalent oxide thickness (EOT) o...

    A. Karamcheti, V. H. C. Watt, T. Y. Luo, D. Brady… in MRS Online Proceedings Library (1999)

  12. No Access

    Article

    Process and Manufacturing Challenges for High-K Gate Stack Systems

    A design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics....

    M. C. Gilmer, T. Y. Luo, H. R. Huff, M. D. Jackson… in MRS Online Proceedings Library (1999)