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  1. No Access

    Chapter

    A Mems Socket Interface For Soc Connectivity

    The design of a system of microelectromechanical (MEMS) sockets that can provide temporary or semi-permanent connectivity to a CMOS System-on-Chip (SoC) environment is presented. The system is comprised of a f...

    Sazzadur Chowdhury, M. Ahmadi, G. A. Jullien… in System-on-Chip for Real-Time Applications (2003)

  2. No Access

    Article

    A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming

    A new algorithm based on Genetic Programming (GP) for the problem of optimization of Multiple constant Multiplication (MCM) by Common Subexpression Elimination(CSE) is developed. This method is used for hardwa...

    H. Safiri, M. Ahmadi, G.A. Jullien… in Journal of VLSI signal processing systems … (2002)

  3. No Access

    Article

    An efficient tree architecture for modulo 2 n +1 multiplication

    Modulo 2 n +1 multiplication plays an important role in the Fermat number transform and residue number systems; the diminished-1 representation of numbers has been found most sui...

    Zhongde Wang, G. A. Jullien, W. C. Miller in Journal of VLSI signal processing systems … (1996)

  4. No Access

    Chapter

    An Intelligent Optical Sensor

    An analog VLSI realization and testing of an intelligent optical sensor is described in this paper. The sensor is designed for the use in process control applications requiring image capture or non-contact mea...

    B. Lam, G. A. Jullien, W. C. Miller in Applications of Photonic Technology (1995)

  5. No Access

    Article

    A fast VLSI systolic array for large modulus residue addition

    The Residue number system (RNS) is inherently suited to high speed computations using custom tailored VLSI systems. In this paper, an algorithm for residue addition, based on a novel, ‘non unique’ number repre...

    S. Bandyopadhyay, G. A. Jullien, A. Sengupta in Journal of VLSI signal processing systems … (1994)

  6. No Access

    Chapter

    Architectures and Building Blocks for Data Stream DSP Processors

    This chapter is concerned with building real-time digital signal processing systems for high throughput, data stream processors. These systems push silicon technology towards its limits, and the architectures ...

    G. A. Jullien in VLSI Design Methodologies for Digital Signal Processing Architectures (1994)

  7. No Access

    Chapter

    High Performance Arithmetic for DSP Systems

    Digital Signal Processing, since its establishment as a discipline 30 years ago, has always received a great impetus from electronic technological advances. It often rides the crest of that wave and sometimes ...

    G. A. Jullien in VLSI Signal Processing Technology (1994)

  8. No Access

    Article

    A low-overhead scheme for testing a bit-level finite ring systolic array

    Testing large VLSI circuits is a difficult and challenging problem for designers. Large unstructured circuits are often impossible to test. The number of test vectors also tend to be large and difficult to gen...

    G. A. Jullien, S. Bandyopadhyay… in Journal of VLSI signal processing systems … (1990)

  9. No Access

    Article

    An efficient bit-level systolic cell design for finite ring digital signal processing applications

    This paper presents design details for a bit-level systolic cell that has been recently introduced for imple menting digital signal processing (DSP) operations over finite rings.

    G. A. Jullien, P. D. Bird, J. T. Carr… in Journal of VLSI signal processing systems … (1989)

  10. No Access

    Article

    Livres reçus

    (H. F.) Harmuth, (A. P.) Clark, (K.) Noda… in Annales des Télécommunications (1987)