Distributed Embedded Smart Cameras
Architectures, Design and Applications
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Domain Isolation and Access Control in Multi-tenant Cloud FPGAs
While sharing FPGA logic in space and time improves hardware utilization and reduces the overall power consumption in FPGA-accelerated clouds, it also raises security concerns. Accelerators from different tena...
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Article
Event camera simulator design for modeling attention-based inference architectures
In recent years, there has been a growing interest in realizing methodologies to integrate more and more computation at the level of the image sensor. The rising trend has seen an increased research interest i...
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Article
Bio-inspired smart vision sensor: toward a reconfigurable hardware modeling of the hierarchical processing in the brain
Biological vision systems inspire processing methods in computer vision applications. This paper employs the insights of vision systems in hardware and presents a pixel-parallel, reconfigurable, and layer-base...
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Article
Hierarchical Design of a Secure Image Sensor with Dynamic Reconfiguration
This paper presents a secure reconfigurable hierarchical hardware architecture at the pixel and region level for smart image sensors to accelerate machine vision applications. The design maintains hierarchical...
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Article
Component interconnect and data access interface for embedded vision applications
IP-based design is used to tackle complexity and reduce time-to-market in systems-on-chip with high-performance requirements. Component integration, the main part in this process, is a complicated and time-con...
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Chapter and Conference Paper
Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip
A novel approach for mitigation of hardware Trojan in Systems on Chip (SoC) is presented. With the assumption that Trojans can cause harm only when they are activated, the goal is to avoid cumbersome and somet...
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Article
Efficient network clustering for traffic reduction in embedded smart camera networks
In this work, a clustering approach for bandwidth reduction in distributed smart camera networks is presented. Properties of the environment such as camera positions and environment pathways, as well as dynam...
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Article
A hardware/software prototy** system for driving assistance investigations
A holistic design and verification environment to investigate driving assistance systems is presented, with an emphasis on system-on-chip architectures for video applications. Starting with an executable speci...
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Chapter and Conference Paper
Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays
In this paper a novel coarse-grained architecture virtualization for Field Programmable Gate Arrays (FPGA) is presented which can be used as basis for run-time dynamic hardware multithreading. The architecture...
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Book
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Multi-modal Sensing for Distracted Driving Mitigation Using Cameras and Crowdsourcing
Driving-related accidents and human casualties are on the rise in the US and around the globe (Brace et al. in Analysis of the literature: the use of mobile phones while driving, 2007). The US government spend...
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Chapter
A Parallel Approach for Statistical Texture Parameter Calculation
This chapter focusses on the development of a new image processing technique for the processing of large and complex images, especially SAR images. We propose here a new and effective approach that outperforms...
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Chapter
Reconfigurable Architectures for Distributed Smart Cameras
Embedded smart cameras must provide enough computational power to handle complex image understanding algorithms on huge amount of data in-situ. In a distributed set-up, smart cameras must provide efficient com...
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Chapter
Design and Verification Environment for High-Performance Video-Based Embedded Systems
In this chapter, we propose a design and verification environment for computational demanding and secure embedded vision-based systems. Starting with an executable specification in OpenCV, we provide subsequen...
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Chapter
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform
Dynamically partially reconfigurable architectures combine high performance and flexibility. They offer a novel possibility to dynamically load and execute hardware modules, previously only known for software ...
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Chapter and Conference Paper
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for parallel programs, thereby alleviating ...
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Article
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
Computer architects have been studying the dynamically reconfigurable computer (Schaumont, Verbauwhede, Keutzer, and Sarrafzadeh, “A Quick Safari through the Reconfiguration Jungle,” in Proc. of the 38th Design A...
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Book
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Chapter and Conference Paper
Embedded Vertex Shader in FPGA
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Chapter and Conference Paper
Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes
