Abstract
For single-electron transfer in common-gate multidot devices, the arrangement of stability regions along the gate voltage (Vg) axis is important because single-electron transfer occurs around the overlap of stability regions. The stability regions along the Vg axis are well known to have periodicity when the device has an integer ratio of gate capacitances (Cg). However, the arrangement rule for the real Cg ratio is unclear. In this paper, stability regions for quadruple-dot devices with symmetric Cg are exhaustively examined. The arrangement of stability regions along the Vg axis is drawn as a map of the real Cg ratio in a newly proposed diagram. Here, the arrangement for a particular Cg ratio is drawn along a straight line that passes through the origin and has a slope depending on the Cg ratio. In the diagram, stability regions are arranged two-dimensionally, and the abovementioned periodicity for integer Cg ratios clearly appears. How neighboring stability regions interrelate with each other in the diagram is mathematically examined and described in detail. Next, the sequences of tunneling events around the overlap of stability regions are investigated, and eight kinds of tunneling sequences for single-electron transfer are determined.
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Energies such as the charging energy and thermal energy can also be normalized by a standard energy e2/Cgt. The thermal effect on CB is unchanged if the temperature and Cgt are changed such that the normalized thermal energy E’th is kept constant, that is, the thermal energy Eth is inversely proportional to Cgt.
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All authors contributed to the study conception and design. Analysis were performed by Shigeru Imai and Yusuke Watanabe. The first draft of the manuscript was written by Shigeru Imai, and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.
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Appendices
Appendix 1
The general formulas of the CB conditions as linear inequalities of Vsd, Vg, and n1 to n4 are described in Appendices A and B of Ref. [25]. In this paper, the junction capacitances are uniform and have a value of Cj. The outer and inner gate capacitances are equal to Cgs and Cgc, respectively. The bias voltages are V0 = −Vsd/2 and V4 = Vsd/2. Then, the formulas are rewritten as follows:
The left side of Eq. (1) is presented as follows:
Here, Q1, Q2, Q3, and Q4 are defined as follows:
The total capacitances are presented as follows, although CT21, CT32, and CT43 are not used in the right-hand sides of Eqs. (16), (17), and (18).
By substituting Eqs. (20)–(24) into Eqs. (15)–(19), the total effective charges are expressed as linear combinations of Vsd, Vg, and n1 to n4. The coefficients in Eqs. (15)–(19) are presented as follows:
\(r_{{{\kern 1pt} {\text{S1}}}} = \frac{{C_{{{\text{Sg1}}}} }}{{C_{{{\text{Sg1}}}} + C_{{{\text{Sg3}}}} }},\quad r_{{{\kern 1pt} {\text{S2}}}} = \frac{{C_{{{\text{Sg2}}}} }}{{C_{{{\text{Sg2}}}} + C_{{{\text{Sg2}}}} }} = \frac{1}{2},\quad r_{{{\kern 1pt} {\text{S3}}}} = \frac{{C_{{{\text{Sg3}}}} }}{{C_{{{\text{Sg3}}}} + C_{{{\text{Sg1}}}} }}.\)
The capacitances CSgi (i = 1–4) in the coefficients are defined as follows, although CSg4 is not used in this paper.
Note that r21R, r32R, r43R, r21L, r32L, r43L, rR21, rR32, rR43, rL12, rL23, and rL34 in Ref. [25] correspond to r3S, r2S, r1S, r1S, r2S, r3S, rS3, rS2, rS1, rS1, rS2, and rS3, respectively. Additionally, CLgi and CRgi in Ref. [25] correspond to CSgi and CSg(5-i), respectively.
Appendix 2
Assume that the bias voltage Vsd = 0. Charges Q1, Q2, Q3, and Q4 can be rewritten by using V′g and V′r as follows because CgtVg = V′g e and 2CgcVg = V′r e:
Then, the effective total charges in Eqs. (15)–(19) are rewritten as follows:
Here, rS1 + rS3 = 1 and rS2 = 1/2 are used to derive Eqs. (32), (33), and (34). The coefficients are presented by using rc as follows:
\(c_{2} = \frac{{1 + r_{{{\kern 1pt} {\text{3S}}}} r_{{{\kern 1pt} {\text{2S}}}} r_{{{\text{1S}}}} }}{2} - \frac{{r_{{{\kern 1pt} {\text{3S}}}} + r_{{{\kern 1pt} {\text{3S}}}} r_{{{\kern 1pt} {\text{2S}}}} }}{2} = \frac{{\left( {26 - r_{{\text{c}}} - r_{c}^{2} } \right)r_{{\text{c}}} }}{{2\left( {44 + 24r_{{\text{c}}} - 3r_{c}^{2} - r_{c}^{3} } \right)}},\)
\(c_{4} = \frac{{r_{{{\kern 1pt} {\text{S3}}}} - r_{{{\kern 1pt} {\text{S1}}}} r_{{{\kern 1pt} {\text{2S}}}} r_{{{\kern 1pt} {\text{1S}}}} }}{2} = \frac{{\left( {26 - r_{{\text{c}}} - r_{{\text{c}}}^{2} } \right)r_{{\text{c}}} }}{{2\left( {60 + 9r_{{\text{c}}} - 5r_{{\text{c}}}^{2} } \right)}},\)
\(c_{6} = \frac{{r_{{{\kern 1pt} {\text{S1}}}} - r_{{{\kern 1pt} {\text{S1}}}} r_{{{\kern 1pt} {\text{2S}}}} }}{2} = \frac{{\left( {3 - r_{{\text{c}}} } \right)\left( {6 + 3r_{{\text{c}}} - r_{{\text{c}}}^{2} } \right)}}{{2\left( {60 + 9r_{{\text{c}}} - 5r_{{\text{c}}}^{2} } \right)}},\)
Equation (33) shows that CT32(V3 − V2) is independent of V′g and V′r, and therefore, only the electron state n determines whether the CB conditions CB23 and CB32 are satisfied at V′sd = 0. When CB23 and CB32 are satisfied at V′sd = 0, the SRR and TSRR exist, and the boundary lines bk(k + 1) and b(k + 1)k for k = 0, 1, 3, and 4 are expressed as follows:
By substituting Eqs. (31)–(35) into Eqs. (36) and (37), Eqs. (7)–(14) are obtained.
For example, when n1 = n4 and n2 = n3, CB23 and CB32 are satisfied because CT32(V3 − V2) = 0. Then, CT10(V1 − V0) = −CT54(V5 − V4) and CT21(V2 − V1) = −CT43(V4 − V3) are satisfied because the third and fourth terms of Eqs. (31), (32), (34), and (35) are zero. Thus, b01(nA) = b54(nA), b45(nA) = b10(nA), b12(nA) = b43(nA), and b34(nA) = b21(nA) are confirmed, and their expressions have been derived.
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Imai, S., Watanabe, Y. Arrangement rule of stability regions and single-electron transfer in common-gate quadruple-dot devices for the real ratio of gate capacitances. J Comput Electron 23, 51–64 (2024). https://doi.org/10.1007/s10825-023-02119-4
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DOI: https://doi.org/10.1007/s10825-023-02119-4