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Two-dimensional materials for electronic applications
This article reviews the potential of graphene and related two-dimensional (2D) materials for applications in micro- and nanoelectronics. In addition...
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Selective epitaxy growth of Si1−xGex layers for MOSFETs and FinFETs
This article reviews the selective epitaxy growth of intrinsic, B- and C-doped SiGe layers on recessed (or flat) exposed Si areas for MOSFETs as well...
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High-Performance, Wide-Bandgap Power Electronics
APEI has developed high-performance electronics to exploit the unique capabilities of wide-bandgap devices. Crucial enabling features include high...
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3D NAND Flash Architectures
Because NAND Flash possesses several advantages such as very high density, low cost, low power consumption, high programming and reading throughput,...
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Graphene Logic Devices and Moore’s Law
The primary semiconductor device is the field-effect transistor, that has evolved with Moore’s Law and is now produced in large scale, reported as...
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Surfactant Mediated Slurry Formulations for Ge CMP Applications
In this study, slurry formulations in the presence of self-assembled surfactant structures were investigated for Ge/SiO 2 CMP applications in the...
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Hybrid orientation technology and strain engineering for ultra-high speed MOSFETs
We report here RF MOSFET performance in sub-45-nm hybrid orientation CMOS technology. Based on the combination of hybrid orientation technology (HOT)...
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Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors
Accumulated body [1] approach to mitigate the effects of line edge roughness on bulk silicon finFETs and tri-gate FETs is analyzed through 3D TCAD...
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Ultrasensitive In-Plane Resonant Nano-electromechanical Sensors
This chapter presents the design, modeling, fabrication, and characterization of in-plane resonant nano-electromechanical (NEM) sensors based on mass...
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Metal–oxide–semiconductor field-effect transistor with a vacuum channel
High-speed electronic devices rely on short carrier transport times, which are usually achieved by decreasing the channel length and/or increasing...
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Atomic Layer Deposition for Nanotechnology
Atomic layer deposition (ALD) is a thin film chemical vapor deposition technology that is uniquely able to deliver extremely conformal, pin hole...
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On-chip tensile testing of nanoscale silicon free-standing beams
Nanomechanical testing of silicon is primarily motivated toward characterizing scale effects on the mechanical behavior. “Defect-free” nanoscale...
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Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below
As device dimensions scale, optimization of the source and drain portions of MOSFETs becomes more important in order to reduce parasitic resistance...
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Atomic Layer Deposition
ALD ; Atomic layer chemical vapor deposition ;...
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Integrated Nanotechnology Based on MEMS
In this chapter, after a brief review of integrated silicon-based MEMS fabrication techniques, MEMS techniques for nano-metric fabrication is...
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Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status
The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges....
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Materials Processing
Materials processing by implantation of energetic ions into solid surfaces has been applied in many fields of modern production technologies. For the...
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Gate contact materials in Si channel devices
Research on contact materials in silicon semiconductor devices has recently gained significant momentum due to the increasing performance demands as...
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Epitaxial Dy2O3 Thin Films Grown on Ge(100) Substrates by Molecular Beam Epitaxy
Dysprosium oxide (Dy 2 O 3 ) films are grown epitaxially on high mobility Ge(100) substrates by molecular beam epitaxy system. Reflection high energy...