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Filter and Comparator Circuits
A comparator compares two voltages and indicate which is larger. A filter is a circuit that separate some frequencies from others. This chapter...
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Comparator Design
In each pipelined ADC stage, the sub-ADC coarsely quantizes the stage input signal. With a robust pipelined ADC architecture and choice of...
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Swift Double-Tail Dynamic Comparator
The requirement for analog to digital with radical less power, more speed and limited area requirement has made the converters to move in the...
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Ultrahigh-Speed High-Sensitivity Dynamic Comparator
The comparator is an important mixed-signal block, both standalone and within an ADC, where its speed determines to a great extent the ADC sample...
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Design of QCA-Based 1-Bit Magnitude Comparator
QCA is a transistor-free method of realizing nanoscale circuit architectures. When compared to the commonly utilized CMOS technology, QCA circuits...
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Design of CNTFET-Based Ternary and Quaternary Magnitude Comparator
This paper presents a novel power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based design of a quaternary magnitude...
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Low-Power High-Speed Modified Three-Stage Comparator with Low Kickback Noise
In this study, a three-level comparator architecture has been suggested to increase speed and decrease kickback noise. The additional amplified stage...
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Torque ripple reduction with modified torque comparator in direct torque-controlled induction motor
The torque ripple (TR) causes vibration in induction motor’s shaft. This TR should be reduced to operate the induction motor drive safely. In this...
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An Energy-efficient and High-speed Dynamic Comparator for Low-noise Applications
An energy-efficient, low-noise, and high-speed dynamic comparator is proposed in this work. The comparator uses two pre-amplifiers to have a...
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Performance Optimization of SAR ADC using Dynamic Controlled Comparator at 45 nm Technology for Biomedical and IoT Applications
The Emerging biomedical applications such as electrocardiography, electroencephalogram, wireless implantable devices have required optimized...
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A Design of ALU Comparator for High Performance RISC-V Processor
In the traditional ALU comparator, in order to generate the result of the comparison instruction, the adder needs to be multiplexed, and the result...
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Design and Analysis of Monopulse Comparator for Tracking Applications
This work presents a design analysis of novel microstrip version of monopulse comparator at Ku band with 10% bandwidth with compact size. The design...
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Run-time reconfigurable nanomagnetic logic gates and comparator designs using very high-permeability material
Nanomagnetic logic is a recent technology used in electronic devices and systems. The current challenge in circuit miniaturization has prompted a...
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Design of Voltage Comparator with High Voltage to Time Gain for ADC Applications
In this paper, a two-stage comparator with high voltage to time gain, low input-referred noise, offset with lesser delay is introduced. The effect of...
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Comparator Design and Effects
Some of the basic issues in the design of comparators are covered including bipolar and MOS-integrated technologies. Also addressed are possibilities...
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Design of Ultralow-Power and High-Speed Comparator Using Charge Sharing Technique
The need for devices with low-power consumption and quick speeds is driven by the advancement of society. Therefore, a high-speed dynamic comparator...
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A Low Noise 10-Bit 59.41dB SNR SAR ADC Using Chopper Comparator for Biomedical Applications
This paper presents a low noise 10-bit 59.51 dB SNR successive-approximation-register (SAR) analog-digital-inverter (ADC) using the chopper...
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Design of Low-Power High-Efficient Single-Tail Comparator Using 180 nm CMOS Technology
Promoting dynamic single-tail comparators to optimize input speed and productivity is the clandestine to low-cost, area-efficient, high-speed analog...
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A Novel Dynamic Latch Comparator Design and Analysis for ADCs
Comparators are used in data converters, sense amplifiers, RFID and data receivers. This paper presents a novel comparator topology for ADC design,...
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Design and analysis of a SET tolerant single-phase clocked double-tail dynamic comparator
A single-event transient tolerant double-tail dynamic comparator is presented and analysed in this paper. The latch stage of the comparator benefited...
