Search
Search Results
-
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm
Arithmetic operations play a substantial role in many applications, such as image processing. In image processing applications, a multiplier is a...
-
Efficient Quantum Circuit for Karatsuba Multiplier
The fundamental element of quantum computing is the quantum circuit. An efficient quantum circuit saves quantum hardware resources by reducing the...
-
A Versatile and Flexible Multiplier Generator for Large Integer Polynomials
This work presents a versatile and flexible generator of various large integer polynomial multipliers to be used in hardware cryptocores. Flexibility...
-
High-Speed and Low-Power Recursive Rounding Based Approximate Multipliers for Error-Resilience Applications
In error-resilience applications, Approximate Multipliers (AMs) play an essential role, having a trade-off between design metrics (DM) and error...
-
Fast Carry-Save Multiplication by Embedded Multipliers on FPGA
This paper proposes a fast scheme for long-precision multiplication based on dedicated or embedded multipliers on FPGAs. It utilizes a group of...
-
Hardware Primitives-Based Accelerator Architecture for NTRU-HRSS Scheme
This paper presents primitives-based accelerator for NTRU-HRSS701 encryption and decryption scheme. The basic primitives to construct the NTRU scheme...
-
Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
The execution of multiplication consumes more time, power and also requires more area than other arithmetic operations. Hence, in floating-point...
-
Fixed-Point Multiplication
Multiplication is the next useful arithmetic building block after addition. In application-specific computing, hardware multipliers are often...
-
IEEE 754 Floating Point Pipelined Multiplier with Karatsuba for Mitigations of Area and Power
The proposed architecture implements IEEE 754 floating point pipelined multiplier merge single and double precision using Karatsuba. This paper is...
-
A 233-Bit Elliptic Curve Processor for IoT Applications
ECC is the most popular asymmetric cipher. It can be used to provide different security services in the IoT applications. This paper presents a...
-
Polynomial Multiplication Architecture with Integrated Modular Reduction for R-LWE Cryptosystems
The ring-learning with errors (R-LWE) problem is the basic building block of many ciphers resisting quantum-computing attacks and homomorphic...
-
Delay Analysis of Hybrid Vedic Multiplier
Vedic mathematics plays a very important role in binary multiplication, in which Karatsuba and Urdhva Tiryagbhyam are most widely used algorithms....
-
Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime
Modular multiplication of long integers is a key component of elliptic curve cryptography and homomorphic encryption. The multiplication complexity...
-
Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks
In this paper, we explore efficient hardware implementation of feedforward artificial neural networks (ANNs) using approximate adders and...
-
Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications
Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed...
-
Trivial Cryptographic Protocol for Resource-Constraint IoT Device Security Using OECC-KA
The IoT structures use data as a general rule; the data arrangement from contraptions can moreover be a goal of cyberattacks. It is a direct result...
-
Comparative analysis of Yavadunam Tavadunikrtya Varganca Yojayet Vedic multiplier for embedded DNN
Memory and computationally efficient CNNs for mobile and embedded applications have sparked a lot of interest recently. Depth-wise and point-wise...
-
Low Power and Complexity Implementation of the Modified FFT with a New Bit-Slicing Scheme
This paper talks over an efficient VLSI realization of the simplified arithmetic radix-2 Decimation In Time (DIT) Fast Fourier Transform (FFT)...
-
Delay-Efficient Vedic Multiplier Design Using 4:3 Counter for Complex Multiplication
Multiplier is one of the functional blocks in the Arithmetic and Logic Unit. Designing a delay-optimized multiplier is always a challenging task at...
-
FPGA-Based Design and Implementation of a Code-Based Post-quantum KEM
Post-quantum cryptography aims to design cryptosystems that can be deployed on traditional computers and resist attacks from quantum computers, which...