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An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions
Process variations within Field Programmable Gate Arrays (FPGAs) provide a rich source of entropy and are therefore well-suited for the...
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Performance-Driven LSTM Accelerator Hardware Using Split-Matrix-Based MVM
This paper proposes a new hardware approach for accelerating matrix vector multiplication (MVM) employing systolic array architecture and parallel...
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Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks
In this paper, we explore efficient hardware implementation of feedforward artificial neural networks (ANNs) using approximate adders and...
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Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network
Hardware Trojans are usually implanted by making malicious changes to a chip circuit, which can destroy chip functions or expose sensitive...
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Analysis and codesign of electronic–photonic integrated circuit hardware accelerator for machine learning application
Innovations in deep learning technology have recently focused on photonics as a computing medium. Integrating an electronic and photonic approach is...
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Research on PPP Time Transfer Method Based on Observable-Specific Signal Bias
Precision time transfer is an integral part of precision time systems, ensuring that multiple clocks maintain high-precision time synchronization....
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Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption
Present complementary metal–oxide–semiconductor (CMOS) technology with scaled channel lengths exhibits higher energy consumption in designing secure...
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Hardware Security of SFQ Circuits
Hardware security of single flux quantum (SFQ) circuits has become an issue of growing importance for prospective exascale computing systems and...
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Design and implementation for a high-efficiency hardware accelerator to realize the learning machine for predicting OLED degradation
A new learning machine based on neural network (NN) and its hardware accelerator are successfully built in this study for predicting the luminance...
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Polymorphic Primitives for Hardware Security
While the previous chapters focused on enabling design automation techniques for Reconfigurable Field-Effect Transistors (RFETs)-based circuits, this...
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Neuromorphic Hardware Accelerators
Despite the tremendous advancements in deep neural network research to achieve Artificial General Intelligence, it continues to suffer from various...
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Architecture for sub-100 ms liquid crystal reconfigurable intelligent surface based on defected delay lines
Reconfigurable intelligent surfaces, comprised of passive tunable elements, are emerging as an essential device for upcoming millimeter wave and...
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Hardware Security in Emerging Photonic Network-on-Chip Architectures
Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of...
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Hardware Security Primitives Based on Emerging Technologies
Due to globalization of the semiconductor industry, outsourcing, and the involvement of multiple vendors over the years, security of integrated...
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Quantifiable Assurance in Hardware
Hardware vulnerabilities are generally considered more difficult to fix than software ones because they are persistent after fabrication. Thus, it is...
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Multiplications to Multipliers: Performing Arithmetic in Hardware
Getting an algorithm from an idea to actual hardware involves major changes in the way we think about numbers. In this chapter, we describe how...
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CAD for Machine Learning in Hardware Security
Machine Learning (ML) has increasingly found its place in a repertoire of tools used in most domains, from speech recognition to self-driving cars....
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Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications
Hardware security has become most prevalent challenging concept of improving the Internet of Things (IoT) in human routine as well as in future...
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Hardware–Software Codesign of an Adder-Tree Type CNN Accelerator
As deep learning applications based on convolutional neural networks (CNNs) are increasingly popular in embedded systems, the demand for a customized...
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Multistable dynamics in a Hopfield neural network under electromagnetic radiation and dual bias currents
This paper investigates a Hopfield neural network under the simulation of external electromagnetic radiation and dual bias currents, in which the...
