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Design and implementation of hardware-efficient architecture for saturation-based image dehazing algorithm
For real-time single-image dehazing, this paper suggests a straightforward and efficient saturation-based transmission map estimation method. For the...
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Hardware architecture optimization for high-frequency zeroing and LFNST in H.266/VVC based on FPGA
To reduce the hardware implementation resource consumption of the two-dimensional transform component in H.266 VVC, a unified hardware structure is...
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A generalized hardware architecture for real-time spiking neural networks
This article presents an area- and power-efficient hardware architecture for the brain-implantable spiking neural networks (SNNs). The proposed...
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Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher
Ensuring data security and integrity is crucial for achieving the highest level of protection and performance in modern cyber-physical systems (CPS)....
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Hardware architecture design for real-time SIFT extraction with reduced memory usage
Scale-invariant feature transform (SIFT) is considered one of the best algorithms to get feature points in an image. It maintains the accuracy in...
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Hardware implementation and validation of the fast variable block size motion estimation architecture for HEVC Standard
High-Efficiency Video Coding (HEVC) has become popular according to its excellent coding performance, in particular in the case of high-resolution...
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Study on versatile video coding multiple transform selection of hardware architecture based on FPGA
The new generation of video coding standard, Versatile Video Coding (VVC), reduces the code stream by 50% at the cost of huge computational...
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Real-time hardware architecture of an ECG compression algorithm for IoT health care systems and its VLSI implementation
The Internet of Things (IoT) in the medical and biomedical field proposes new and efficient hardware for healthcare services. Thanks to...
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Hardware architecture and memristor-crossbar implementation of type-2 fuzzy system with type reduction and in-situ training
The Type-2 fuzzy set is a fuzzy set with fuzzy membership degrees. This set is used when accurately determining the membership degree of a fuzzy set...
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Universal Gaussian elimination hardware for cryptographic purposes
In this paper, we investigate the possibility of performing Gaussian elimination for arbitrary binary matrices on hardware. In particular, we...
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A new hardware architecture of lightweight and efficient real-time video chaos-based encryption algorithm
In this paper, we propose a novel chaotic-based encryption scheme for securing real-time video data. The proposed encryption algorithm is based on...
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An improved residual learning model and its application to hardware image classification
Some hardware is similar in color and shape between different classes, and some hardware varies within a class, thereby decreasing the accuracy of...
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Hardware implementation of digital pseudo-random number generators for real-time applications
This paper introduces the hardware implementation of Digital Pseudo-Random Number Generators (DPRNG) based on chaotic systems. First,...
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A novel trusted hardware-based scalable security framework for IoT edge devices
The Internet of Things (IoT) devices are pervasively deployed and embedded into our daily lives. Over several years, the massive assimilation of IoT...
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HILP: hardware-in-loop pruning of convolutional neural networks towards inference acceleration
Successful deployment of convolutional neural networks on resource-constrained hardware platforms is challenging for ubiquitous AI applications. For...
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Hardware Architecture for GRAND with ABandonment (GRANDAB)
This chapter presents a high-throughput and energy-efficient hardware architecture for the GRAND with ABandonment (GRANDAB) decoder, a hard-input...
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Hardware Architecture for Ordered Reliability Bits GRAND (ORBGRAND)
Ordered Reliability Bits GRAND (ORBGRAND) is a soft-input GRAND variant that has superior decoding performance than the hard-input GRANDAB. The...
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Dedicated hardware design for efficient quantum computations using classical logic gates
This work presents a novel approach to quantum computing by proposing a customizable hardware design of a dedicated processor that emulates the...
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Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology
The purpose of this research topic is to investigate the properties of reconfigurable devices (i.e., FPGA) under a radiation environment to finally...
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High-speed hardware accelerator based on brightness improved by Light-DehazeNet
Due to the increasing demand for artificial intelligence technology in today’s society, the entire industrial production system is undergoing a...
