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  1. No Access

    Chapter and Conference Paper

    Cache Controller Design on Ultra Low Leakage Embedded Processors

    A leakage-efficient cache controller design targeted on ultra low power embedded processors is proposed. The key insight is that a large circuits subset is accessed only when cache misses happen. By utilizing ...

    Zhao Lei, Hui Xu, Naomi Seki, Saito Yoshiki… in Architecture of Computing Systems – ARCS 2… (2009)

  2. No Access

    Chapter and Conference Paper

    Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor

    The Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor with the capability of changing its hardware functionality within a clock cycle. While imp...

    Vu Manh Tuan, Yohei Hasegawa… in Reconfigurable Computing: Architectures an… (2006)

  3. Chapter and Conference Paper

    Fast and Secure Packet Processing Environment for Per-Packet QoS Customization

    To allow end users define network behavior andto make communication network evolution service-driven, we propose fast and secure capsule processing environment, dedicated CPU architecture named StreamCode and ...

    Takashi Egawa, Koji Hino, Yohei Hasegawa in Active Networks (2001)

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