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17 Result(s)
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Shi-yu **ang
Circuits and Systems
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Article
Instant Test and Repair for TSVs using Differential Signaling
A faulty Through Silicon Via (TSV) could spoil a 3D IC and cause hefty loss as the potentially expensive known-good-dies bonded together must be discarded. This work presents a Fault-tolerant TSV scheme to avo...
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Article
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme
A Phase-Locked Loop (PLL) is indispensable in producing high-speed on-chip clock signals in an IC. For safety–critical applications, fault and soft-error tolerance are often desirable. However, how to achieve ...
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Chapter and Conference Paper
Research on Radar Anti-jamming Performance Evaluation System in Complex Electromagnetic Environment
There are problems of large limitations and different standards in the evaluation of interference resistance performance of radar and other information equipment in complex electromagnetic environments. We con...
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Article
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are n...
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Article
A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis
Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine General's phenomenon, in whic...
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Book
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Chapter
Introduction
Hardware verification is a process of checking if a design conforms to its specifications of functionality, timing, testability, and power dissipation. Among these criteria, functional verification has the hig...
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Chapter
RTL-to-Gate Verification
In this chapter we discuss the use of a gate-to-gate equivalence checker to verify a gate-level implementation against its structural RTL specification. We begin with the basic methodology for RTL-to-gate veri...
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Chapter
Extension to Sequential Error Diagnosis
This chapter extends the fault-simulation-based diagnosis approach to sequential circuits. We first describe the necessary and sufficient condition of a correctable input sequence that can be corrected by changin...
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Chapter
Algorithm for Verifying Retimed Circuits
In this chapter, we discuss a heuristic for verifying retimed circuits. Usually after the retiming transformation, some flip-flops or latches in a sequential circuit are re-positioned. Thus, the behavior of th...
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Chapter
Incremental Verification for Combinational Circuits
In this chapter we discuss the incremental algorithms that explore the structural similarity between two circuits to speed up the verification process. Three types of algorithms, namely substitution-based, lea...
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Chapter
AQUILA: A Local BDD-based Equivalence Verifier
In this chapter we describe the enhancement of the ATPG-based framework by local BDD-based techniques. This enhancement involves two ideas. First, we generalize the inductive algorithm of Section 4.3 to identi...
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Chapter
ErrorTracer: Error Diagnosis by Fault Simulation
In this chapter we discuss a method for combinational design error diagnosis. We introduce a fault-simulation-based technique to approximate each signal’s correcting power. The correcting power of a signal is ...
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Chapter
Symbolic Verification
In this chapter we discuss symbolic algorithms that rely on finite state machine (FSM) traversal to perform equivalence checking. FSM traversal is a process that explores the state space of a finite state mach...
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Chapter
Introduction to Logic Debugging
In this chapter we review a number of representative algorithms for error diagnosis and correction. For error diagnosis, we discuss methods of locating the error sources in an incorrect combinational implement...
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Chapter
Incremental Logic Rectification
Both engineering change and error correction can be formulated as a logic rectification problem. This problem takes two gate-level netlists, which are functionally inequivalent, as inputs. One is considered as...
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Chapter
Incremental Verification for Sequential Circuits
In this chapter we address the problem of verifying the equivalence of two sequential circuits. In an attempt to handle larger circuits, we modify the test pattern generation technique for verification. The su...
