7 Result(s)
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Article
Open AccessA Practical Approach for Employing Tensor Train Decomposition in Edge Devices
Deep Neural Networks (DNN) have made significant advances in various fields including speech recognition and image processing. Typically, modern DNNs are both compute and memory intensive, therefore their depl...
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Article
A Methodology for Efficient Tile Size Selection for Affine Loop Kernels
Reducing the number of data accesses in memory hierarchy is of paramount importance on modern computer systems. One of the key optimizations addressing this problem is loop tiling, a well-known loop transforma...
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Chapter
Accelerating AAL Home Services Using Embedded Hardware Components
The EU-funded project RADIO brings forward a new healthcare paradigm according to which a mobile robotic platform can act as an assistant to an person in his/her domestic environment. The main goal of the ro...
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Article
Revisiting Cache Resizing
We present a novel framework to dynamically reconfigure on-chip memory resources according to the changing behavior of the executing applications. Our framework enables smooth scaling (i.e., resizing) of the o...
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Chapter
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches
In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open the possibility to unify dynamic and l...
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Chapter and Conference Paper
Applying Decay to Reduce Dynamic Power in Set-Associative Caches
In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open the possibility to unify dynamic and l...
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Chapter and Conference Paper
Preventing Denial-of-Service Attacks in Shared CMP Caches
Denial-of-Service (DoS) attacks try to exhaust some shared resources (e.g. process tables, functional units) of a service-centric provider. As Chip Multi-Processors (CMPs) are becoming mainstream architecture ...
