Advanced Parallel Processing Technologies
12th International Symposium, APPT 2017, Santiago de Compostela, Spain, August 29, 2017, Proceedings
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10 Result(s)
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Chapter and Conference Paper
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks
Graph neural networks (GNNs) have attracted increasing interests in recent years. Due to the poor data locality and huge data movement during GNN inference, it is challenging to employ GNN to process large-sca...
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Book and Conference Proceedings
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Book
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Chapter
Conclusions
As the technologies scale down, the memory hierarchy implemented with traditional memory technologies cannot satisfy the requirements of high performance, low power, and high reliability.
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Chapter
Introduction
In this section, we introduce several challenges, by which the leverage of emerging technologies are motivated. From the architectural view, we first discuss the increasing requirement of on-chip memory and ba...
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Chapter
Moguls: A Model to Explore the Memory Hierarchy for Throughput Computing
Throughput computing(TC) refers to trading off latency or single-thread performance for higher overall computational throughput. Throughput computing involves performing a huge number of calculations with a la...
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Chapter
A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement
In recent years, many systems have employed NAND flash memory as storage devices because of its advantages of high I/O performance, increasing capacity, and falling cost. On the other hand, the performance of ...
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Chapter
Replacing Different Levels of the Memory Hierarchy with NVMs
As the first step of exploring the usage of various NVMs in different levels of the memory hierarchy, we compare the NVMs with memories used in the traditional memory hierarchy, as shown in Fig. 2.1.
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Chapter
Exploring the Vulnerability of CMPs to Soft Errors with 3D Stacked Non-Volatile Memory
Due to the continuously reduced feature size, supply voltage, and increased on-chip density, modern microprocessors are projected to be more susceptible to soft error strikes.
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Chapter
An Energy-Efficient 3D Stacked STT-RAM Cache Architecture for CMPs
In this chapter, we introduce how to adopt spin-transfer torque random access memory (STT-RAM) as on-chip L2 caches to achieve better performance and lower energy consumption, compared to traditional L2 cache ...
