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Chapter and Conference Paper
On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs
OpenCL is used in contemporary FPGA High-level Synthesis (HLS) design tools for the development of the host-side code which controls the data transfer between the processing system and the FPGA design. High pe...
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Chapter and Conference Paper
A Comparative Study of Neural Network Compilers on ARMv8 Architecture
The deployment of Deep Neural Network (DNN) models in far edge devices is a challenging task, because these devices are characterized by scarce resources. To address these challenges various deep learning tool...
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Chapter and Conference Paper
A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices
Deep Neural Networks (DNN) have made significant advances in various fields, including speech recognition and image processing. Typically, modern DNNs are both compute and memory intensive and as a consequence...
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Chapter and Conference Paper
An Analytical Model for Loop Tiling Transformation
Loop tiling is a well-known loop transformation that enhances data locality in memory hierarchy. In this paper, we initially reveal two important inefficiencies of current analytical loop tiling models and we ...
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Chapter
Accelerating AAL Home Services Using Embedded Hardware Components
The EU-funded project RADIO brings forward a new healthcare paradigm according to which a mobile robotic platform can act as an assistant to an person in his/her domestic environment. The main goal of the ro...
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Chapter and Conference Paper
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience
Demographic and epidemiologic transitions have brought a new health care paradigm where life expectancy is increasing as well as the need for long-term care. To meet the resulting challenge, healthcare systems...
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Chapter and Conference Paper
Erratum to: Applied Reconfigurable Computing
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Chapter
VirISA: Recruiting Virtualization and Reconfigurable Processor ISA for Malicious Code Injection Protection
As users place increasingly more sensitive information in IT products, trusting that a system is not compromised by malicious entities becomes imperative. Code injection is a well-known attack that can directl...
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Chapter
IoT in Ambient Assistant Living Environments: A View from Europe
The purpose of this chapter is to offer a survey of the EU funded projects within the scope of Internet of Things and ambient assisted living (AAL) environments. Our analysis concentrates on three main aspects...
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Chapter and Conference Paper
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective
Demographic and epidemiologic transitions in Europe have brought a new health care paradigm where life expectancy is increasing as well as the need for long-term care. To meet the resulting challenge, European...
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Chapter
From Hardware Security Tokens to Trusted Computing and Trusted Systems
As security attacks are becoming an everyday real-life scenario, security engineers must invent more intricate countermeasures to deal with them. Infusion of strong security to a computer system by recruiting ...
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Chapter
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches
In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open the possibility to unify dynamic and l...
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Chapter and Conference Paper
Applying Decay to Reduce Dynamic Power in Set-Associative Caches
In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open the possibility to unify dynamic and l...
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Chapter and Conference Paper
Dynamic Dictionary-Based Data Compression for Level-1 Caches
Data cache compression is actively studied as a venue to make bet ter use of on-chip transistors, increase apparent capacity of caches, and hide the long memory latencies. While several techniques have been pr...
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Chapter and Conference Paper
Preventing Denial-of-Service Attacks in Shared CMP Caches
Denial-of-Service (DoS) attacks try to exhaust some shared resources (e.g. process tables, functional units) of a service-centric provider. As Chip Multi-Processors (CMPs) are becoming mainstream architecture ...